WM8281ECSSLASHR datasheet(104/392 Pages) CIRRUS

104 / 392 page

WM8281

104

Rev 4.0

OUT6R output

OUT6L output

OUT5R output

OUT5L output

OUT4R output

OUT4L output

OUT3R output

OUT3L output

OUT2R output

OUT2L output

OUT1R output

OUT1L output

AIF1 TX8 output

AIF1 TX7 output

AIF1 TX6 output

AIF1 TX5 output

AIF1 TX4 output

AIF1 TX3 output

AIF1 TX2 output

AIF1 TX1 output

AIF1 RX3 (22h)

AIF1 RX4 (23h)

AIF1 RX5 (24h)

AIF1 RX6 (25h)

AIF1 RX7 (26h)

AIF1 RX8 (27h)

AIF1 RX1 (20h)

AIF1 RX2 (21h)

SLIMbus TX8 output

SLIMbus TX7 output

SLIMbus TX6 output

SLIMbus TX5 output

SLIMbus TX4 output

SLIMbus TX3 output

SLIMbus TX2 output

SLIMbus TX1 output

SLIMbus RX3 (3Ah)

SLIMbus RX4 (3Bh)

SLIMbus RX5 (3Ch)

SLIMbus RX6 (3Dh)

SLIMbus RX7 (3Eh)

SLIMbus RX8 (3Fh)

SLIMbus RX1 (38h)

SLIMbus RX2 (39h)

AIF1_RATE

AIF3_RATE

AIF2_RATE

OUT_RATE

SLIMTX1_RATE

SLIMTX2_RATE

SLIMTX3_RATE

SLIMTX4_RATE

SLIMTX5_RATE

SLIMTX6_RATE

SLIMTX7_RATE

SLIMTX8_RATE

SLIMRX1_RATE

SLIMRX2_RATE

SLIMRX3_RATE

SLIMRX4_RATE

SLIMRX5_RATE

SLIMRX6_RATE

SLIMRX7_RATE

SLIMRX8_RATE

AIF3 TX2 output

AIF3 TX1 output

AIF3 RX1 (30h)

AIF3 RX2 (31h)

AIF2 TX6 output

AIF2 TX5 output

AIF2 TX4 output

AIF2 TX3 output

AIF2 TX2 output

AIF2 TX1 output

AIF2 RX3 (2Ch)

AIF2 RX4 (2Dh)

AIF2 RX5 (2Eh)

AIF2 RX6 (2Fh)

AIF2 RX1 (2Ah)

AIF2 RX2 (2Bh)

Figure 39 Digital Core Sample Rate Control (External Digital Interfaces)

The input signal paths may be selected as input to the digital mixers or signal processing functions.

The sample rate for the input signal paths is configured using the IN_RATE register.

The output signal paths are derived from the respective output mixers. The sample rate for the output

signal paths is configured using the OUT_RATE register. The sample rate of the AEC Loopback path

is also set by the OUT_RATE register.

The AIFn RX inputs may be selected as input to the digital mixers or signal processing functions. The

AIFn TX outputs are derived from the respective output mixers. The sample rates for digital audio

interfaces (AIF1, AIF2 and AIF3) are configured using the AIF1_RATE, AIF2_RATE and AIF3_RATE

registers respectively.

The SLIMbus interface supports up to 8 input channels and 8 output channels. The sample rate of

each channel can be configured independently, using the SLIMTXn_RATE and SLIMRXn_RATE

registers.

Note that the SLIMbus interface provides simultaneous support for SYSCLK-referenced and

ASYNCCLK-referenced sample rates on different channels. For example, 48kHz and 44.1kHz

SLIMbus audio paths can be simultaneously supported.

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