WM8281ECSSLASHR datasheet(141/392 Pages) CIRRUS

141 / 392 page

WM8281

Rev 4.0

141

DIGITAL AUDIO INTERFACE

The WM8281 provides three audio interfaces, AIF1, AFI2 and AIF3. Each of these is independently

configurable on the respective transmit (TX) and receive (RX) paths. AIF1 supports up to 8 channels

of input and output signal paths; AIF2 supports up to 6 channels of input and output signal paths; AIF3

supports up to 2 channels of input and output signal paths.

The data source(s) for the audio interface transmit (TX) paths can be selected from any of the

WM8281 input signal paths, or from the digital core processing functions. The audio interface receive

(RX) paths can be selected as inputs to any of the digital core processing functions or digital core

outputs. See “Digital Core” for details of the digital core routing options.

The digital audio interfaces provide flexible connectivity for multiple processors and other audio

devices. Typical connections include Applications Processor, Baseband Processor and Wireless

Transceiver. Note that the SLIMbus interface also provides digital audio input/output paths, providing

options for additional interfaces. A typical configuration is illustrated in Figure 42.

The audio interfaces AIF1, AIF2 and AIF3 are referenced to DBVDD1, DBVDD2 and DBVDD3

respectively, allowing the WM8281 to connect between application sub-systems on different voltage

domains.

Audio Interface 1

Audio Interface 2

Audio Interface 3

HDMI

Device

Baseband

Processor

Wireless

Transceiver

WM8281

SLIMbus interface

Applications

Processor

Figure 42 Typical AIF Connections

In the general case, the digital audio interface uses four pins:



TXDAT: Data output



RXDAT: Data input



BCLK: Bit clock, for synchronisation



LRCLK: Left/Right data alignment clock

In master interface mode, the clock signals BCLK and LRCLK are outputs from the WM8281. In slave

mode, these signals are inputs, as illustrated below.

As an option, a GPIO pin can be configured as TXLRCLK, ie. the Left/Right clock for the TXDAT

output. In this case, the LRCLK pin is dedicated to the RXDAT input, allowing the two sides to be

clocked independently.

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