WM8281ECSSLASHR datasheet(137/392 Pages) CIRRUS

137 / 392 page

WM8281

Rev 4.0

137

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5168

(1430h)

DSP4

WDMA

Config 1

13:0

DSP4_WDMA_B

UFFER_LENGTH

[13:0]

0000h

DSP4 DMA Buffer Length

Selects the amount of data transferred in

each WDMA channel. The LSB represents

one 24-bit DSP memory word.

R5169

(1431h)

DSP4

WDMA

Config 2

7:0

DSP4_WDMA_C

HANNEL_ENABL

E [7:0]

00h

DSP4 WDMA Channel Enable

There are 8 WDMA channels; each bit of

this field enables the respective WDMA

channel.

Each bit is coded as:

0 = Disabled

1 = Enabled

R5170

(1432h)

DSP4

WDMA

Offset 1

7:0

DSP4_WDMA_C

HANNEL_OFFSE

T [7:0]

00h

DSP4 WDMA Channel Offset

There are 8 WDMA channels; each bit of

this field offsets the Start Address of the

respective WDMA channel.

Each bit is coded as:

0 = No offset

1 = Offset by 8000h

R5172

(1434h)

DSP4

RDMA

Config 1

5:0

DSP4_RDMA_C

HANNEL_ENABL

E [5:0]

00h

DSP4 RDMA Channel Enable

There are 6 RDMA channels; each bit of

this field enables the respective RDMA

channel.

Each bit is coded as:

0 = Disabled

1 = Enabled

R5173

(1435h)

DSP4

RDMA

Offset 1

5:0

DSP4_RDMA_C

HANNEL_OFFSE

T [5:0]

00h

DSP4 RDMA Channel Offset

There are 6 RDMA channels; each bit of

this field offsets the Start Address of the

respective RDMA channel.

Each bit is coded as:

0 = No offset

1 = Offset by 8000h

Table 29 DSP Direct Memory Access (DMA) Control

DSP DEBUG SUPPORT

General purpose ‘scratch’ registers are provided for each DSP. These have no assigned function, and

can be used to assist in algorithm development.

The JTAG interface provides test and debug access to the WM8281

, as described in the “JTAG

Interface

” section. The JTAG interface clock can be enabled independently for each DSP core, using

the DSPn_DBG_CLK_ENA register bits.

When using the JTAG interface to access any DSP core, the respective DSPn_DBG_CLK_ENA,

DSPn_SYS_ENA, and DSPn_CORE_ENA bits must all be set.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4352

(1100h)

DSP1

Control 1

DSP1_DBG_CLK

_ENA

DSP1 Debug Clock Enable

0 = Disabled

1 = Enabled

R4416

(1140h)

DSP1

Scratch 0

15:0

DSP1_SCRATCH

_0 [15:0]

0000h

DSP1 Scratch Register 0

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