WM8281ECSSLASHR datasheet(178/392 Pages) CIRRUS

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WM8281

178

Rev 4.0

SLIMBUS CLOCKING CONTROL

The clock frequency of the SLIMbus interface is not fixed, and may be set according to the application

requirements. The clock frequency can be reconfigured dynamically as required.

The WM8281 SLIMbus interface includes a Framer Device. When configured as the active Framer,

the SLIMbus clock (SLIMCLK) is an output from the WM8281. At other times, SLIMCLK is an input.

The Framer function can be transferred from one device to another; this is known as Framer

Handover, and is controlled by the Manager Device.

The supported Root Frequencies in Active Framer mode are 24.576MHz or 22.5792MHz only. At

other times, the supported Root Frequencies are as defined in the MIPI Alliance specification for

SLIMbus.

Under normal operating conditions, the SLIMbus interface operates with a fixed Root Frequency (RF);

dynamic updates to the bus rate are applied using a selectable Clock Gear (CG) function. The Root

Frequency and the Clock Gear setting are controlled by the Manager Device; these parameters are

transmitted in every SLIMbus superframe to all devices on the bus.

In Gear 10 (the highest Clock Gear setting), the SLIMCLK input (or output) frequency is equal to the

Root Frequency. In lower gears, the SLIMCLK frequency is reduced by increasing powers of 2.

The Clock Gear definition is shown in Table 58. Note that 24.576MHz Root Frequency is an example

only; other frequencies are also supported.

CLOCK GEAR

DESCRIPTION

SLIMCLK FREQUENCY

(

assuming 24.576MHz Root Frequency)

Divide by 1

24.576MHz

Divide by 2

12.288MHz

Divide by 4

6.144MHz

Divide by 8

3.072MHz

Divide by 16

1.536MHz

Divide by 32

768kHz

Divide by 64

384kHz

Divide by 128

192kHz

Divide by 256

96kHz

Divide by 512

48kHz

Table 58 SLIMbus Clock Gear Selection

When the WM8281 is the active Framer, the SLIMCLK output is synchronised to the SYSCLK or

ASYNCCLK system clock, as selected by the SLIMCLK_SRC register bit.

The applicable system clock must be enabled, and configured at the SLIMbus Root Frequency,

whenever the WM8281 is the active Framer.

See “Clocking and Sample Rates” for details of the

SYSCLK and ASYNCCLK system clocks.

When the WM8281 is not configured as the active Framer device, then the SLIMCLK input can be

used to provide a reference source for the Frequency Locked Loops (FLLs). The frequency of this

reference is controlled using the SLIMCLK_REF_GEAR register, as described in Table 59.

The SLIMbus clock reference is generated using an adaptive divider on the SLIMCLK input. The

divider automatically adapts to the SLIMbus Clock Gear (CG).

Note that, if the Clock Gear (CG) on the bus is lower than the SLIMCLK_REF_GEAR, then the

selected reference frequency cannot be supported, and the SLIMbus clock reference is disabled.

The SLIMbus clock reference is selected as input to the FLLs using the FLLn_REFCLK_SRC

registers. See “Clocking and Sample Rates” for details of system clocking and the FLLs.

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