WM8281ECSSLASHR datasheet(182/392 Pages) CIRRUS

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WM8281

182

Rev 4.0

OUTPUT SIGNAL PATH ENABLE

The output signal paths are enabled using the register bits described in Table 61. The respective

bit(s) must be enabled for analogue or digital output on the respective output path(s).

The output signal paths are muted by default. It is recommended that de-selecting the mute should be

the final step of the path enable control sequence. Similarly, the mute should be selected as the first

step of the path disable control sequence. The output signal path mute functions are controlled using

the register bits described in Table 64.

The supply rails for outputs (OUT1, OUT2 and OUT3) are generated using an integrated dual-mode

Charge Pump, CP1. The Charge Pump is enabled automatically by the WM8281 when required by

the output drivers

. See the “Charge Pumps, Regulators and Voltage Reference” section for further

details.

The WM8281 schedules a pop-suppressed control sequence to enable or disable the OUT1, OUT2

OUT3 and OUT4 signal paths. This is automatically managed in response to setting the respective

HPnx_ENA or SPKOUTx_ENA register bits.

See “Control Write Sequencer” for further details.

The headphone output (OUT1, OUT2, OUT3) enable control sequences are inputs to the Interrupt

circuit, and can be used to trigger an Interrupt event when a sequence completes. See “Interrupts” for

further details.

The headphone output (OUT1, OUT2, OUT3) enable control sequences can also generate a GPIO

output, providing an external indication of the sequence status. See “General Purpose Input / Output”

to configure a GPIO pin for this function.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The

ASYNCCLK may also be required, depending on the path configuration. See “Clocking and Sample

Rates

” for details of the system clocks.

The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to

support the output signal paths and associated DACs. If an attempt is made to enable an output

signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be

unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See

“General Purpose Input / Output” and “Interrupts” for further details.

The status bits in Register R1025 and R1030 indicate the status of each of the output signal paths. If

an Underclocked Error condition occurs, then these bits provide readback of which signal path(s)

have been successfully enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1024

(0400h)

Output

Enables 1

OUT6L_ENA

Output Path 6 (Left) Enable

0 = Disabled

1 = Enabled

OUT6R_ENA

Output Path 6 (Right) Enable

0 = Disabled

1 = Enabled

OUT5L_ENA

Output Path 5 (Left) Enable

0 = Disabled

1 = Enabled

OUT5R_ENA

Output Path 5 (Right) Enable

0 = Disabled

1 = Enabled

SPKOUTL_ENA

Output Path 4 (Left) Enable

0 = Disabled

1 = Enabled

SPKOUTR_ENA

Output Path 4 (Right) Enable

0 = Disabled

1 = Enabled

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