WM8281ECSSLASHR datasheet(220/392 Pages) CIRRUS

220 / 392 page

WM8281

220

Rev 4.0

LOW POWER SLEEP CONFIGURATION

The WM8281 supports a low-

power ‘Sleep’ mode, where most functions are disabled, and power

consumption is minimised. A selectable ‘Wake-Up’ event can be configured to return the device to full

operation and/or execute a specific response to the particular Wake-Up condition.

A Wake-Up event is triggered via hardware input pin(s); in typical applications, these inputs are

associated with jack insert (via the JACKDET analogue input) or external push-button detection (via

the GPIO5 digital input). A Wake-Up transition can also be triggered using the LDOENA pin to enable

LDO1 (assuming that DCVDD is supplied by LDO1).

The WM8281 enters Sleep mode when LDO1 is disabled, causing the DCVDD supply to be removed.

The AVDD, DBVDD1, and LDOVDD supplies must be present throughout the Sleep mode duration.

Note that it is assumed that DCVDD is supplied by LDO1; s

ee the “Charge Pumps, Regulators and

Voltage Reference

” for specific control requirements where DCVDD is not powered from LDO1.

SLEEP MODE

The WM8281 enters Sleep mode when LDO1 is disabled, causing the DCVDD supply to be removed.

(LDO1 can be controlled using the LDO1_ENA register bit, or using the LDOENA pin; both of these

controls must be de-asserted to disable the LDO. Note that, under certain circumstances -

see “Write

Sequence Control

” below - the LDO is controlled by writing to the _TRIG_STS register fields.) The

AVDD, DBVDD1, and LDOVDD supplies must be present throughout the Sleep mode; under these

conditions, and with LDO1 disabled, most of the Digital Core (and control registers) are held in reset.

For correct Sleep mode behaviour, the following register configuration is required before entering the

Sleep mode:



Write the value A210h to Register R13056 (3300h), and write 050Ch to Register R13057

(3301h). Note that SYSCLK must be enabled when writing to these registers. These

is not necessary to repeat these register writes before each Sleep transition.



Write the value 0Bh to the LDO1_VSEL field in Register R528 (0210h). This register write is

required before every Sleep transition, and must be scheduled as the last register write

before whichever final action is used to command the WM8281 to Sleep mode. See

“Charge Pumps, Regulators and Voltage Reference” for details of the LDO1_VSEL field.

Note that it is assumed that DCVDD is supplied by LDO1; see the “Charge Pumps, Regulators and

Voltage Reference

” for specific control requirements where DCVDD is not powered from LDO1.

The system clocks (SYSCLK, ASYNCCLK) are not required in Sleep mode, and the external clock

inputs (MCLKn) may be stopped, except as described below.

If de-bounce is enabled on any of the configured Wake-Up signals (JACKDET or GPIO5), then the

32kHz clock must be active during Sleep mode (see “Clocking and Sample Rates”). The 32kHz clock

must be derived from the MCLK2 pin in this case. The 32kHz clock must be configured using

CLK_32K_ENA and CLK_32K_SRC before Sleep mode is entered.

The MCLK2 frequency limit in Sleep mode (see “Signal Timing Requirements”) must be observed

before entering Sleep mode, and maintained until after Wake-Up.

Selected functions and control registers are maintained via an

‘Always-On’ internal supply domain in

Sleep mode. The ‘Always-On’ control registers are listed in Table 81. These registers are maintained

(ie. not reset) in Sleep mode.

The CLK32K_ENA and CLK_32K_SRC registers are maintained in Sleep mode, but are reset to

default values on Wake-Up. The WM8281 can be configured to enable the 32kHz clock (derived from

MCLK2) automatically on Wake-Up; this may typically be required in applications where the 32kHz

clock has been maintained in Sleep mode. To enable the 32kHz clock on Wake-Up, write the value

C100h to Register R14202 (337Ah), and write 0041h to Register R14203 (337Bh). Note that SYSCLK

must be enabled when writing to these registers.

Note that the Control Interface is not supported in Sleep mode. Read/Write access to the ‘Always-On’

registers is not possible in Sleep mode.

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