WM8281ECSSLASHR datasheet(223/392 Pages) CIRRUS

223 / 392 page

WM8281

Rev 4.0

223

A Wake-Up transition is triggered using the JD1 or GP5 control signals (defined below).

It is assumed that DCVDD is supplied by LDO1. The AVDD, DBVDD1 and LDOVDD supplies must be

present throughout the Sleep mode duration

. See “Charge Pumps, Regulators and Voltage

Reference

” for specific control requirements where DCVDD is not powered from LDO1.

Note that a logic ‘1’ applied to the LDOENA pin will also cause a Wake-Up transition. In this event,

however, the configurable Wake-Up events (described below) are not applicable.

SLEEP CONTROL SIGNALS - JD1, GP5, MICDET CLAMP

The internal control signals JD1 and GP5 are provided to support the low-power Sleep mode. The

MICDET Clamp status is controlled by a selectable logic function, derived from JD1 and/or GP5. A

rising or falling edge of these signals can be used to trigger a Wake-Up transition (ie. exit from Sleep

mode).

The JD1, GP5 and MICDET Clamp status signals can also be used to trigger the Control Write

Sequencer and/or the Interrupt Controller.

Note that it is possible to enable more than one response from these control signals. For example, a

particular edge transition could trigger a Wake-Up transition, and also a Control Write Sequence.

The JD1, GP5 and MICDET Clamp status signals are described in this section. The Wake-Up, Write

Sequencer, and Interrupt actions are described in the sections that follow.

The JD1 signal is derived from the Jack Detect function (see “External Accessory Detection”). This

input can be used to trigger Wake-Up or other actions in response to a jack insertion or jack removal

detection.

When the JD1 signal is enabled, it indicates the status of the JACKDET input pin. See Table 75 for

details of the associated control registers.

The GP5 signal is derived from the GPIO5 input pin (see “General Purpose Input / Output”). This input

can be used to trigger Wake-Up or other actions in response to a logic level input detected on the

GPIO5 pin.

When using the GP5 signal, the GPIO5 pin must be configured as a GPIO input (GP5_DIR=1,

GP5_FN=01h). An internal pull-up or pull-down resistor may be enabled on the GPIO5 pin if required.

The GPIO pin control registers are defined in Table 86.

The MICDET Clamp

status is controlled by the JD1 and/or GP5 signals (see “External Accessory

Detection

”). The configurable logic provides flexibility in selecting the appropriate conditions for

activating the MICDET Clamp. The clamp status can be used to trigger Wake-Up or other actions in

response to a jack insertion or jack removal detection.

The MICDET Clamp function is configured using the MICD_CLAMP_MODE register, as described in

Table 76.

Whenever a rising or falling edge is detected on JD1, GP5 or MICDET Clamp status, the WM8281 will

assert the respective trigger status (_TRIG_STS) bit. The trigger status bits are latching fields and,

once they are set, they are not reset until a ‘1’ is written to the respective register bit(s).

The JD1, GP5 and MICDET Clamp trigger status bits are described in Table 83.

The trigger status bits can be used to control Wake-Up and Write Sequencer actions. The JD1, GP5

and MICDET Clamp signals are inputs to the Interrupt Controller. Each of these functions is described

in the following sections.

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