WM8281ECSSLASHR datasheet(251/392 Pages) CIRRUS

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WM8281

Rev 4.0

251

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

HP2L_SC_NEG_

EINT1

HPOUT2L Short Circuit Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

HP2L_SC_POS_

EINT1

HPOUT2L Short Circuit Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

HP1R_SC_NEG_

EINT1

HPOUT1R Short Circuit Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

HP1R_SC_POS_

EINT1

HPOUT1R Short Circuit Interrupt

(Rising edge triggered)

Note:

Cleared when a ‘1’ is written.

HP1L_SC_NEG_

EINT1

HPOUT1L Short Circuit Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

HP1L_SC_POS_

EINT1

HPOUT1L Short Circuit Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

R3336

(0D08h)

R3341

(0D0Dh)

IM_*

(see note)

For each *_EINT1 interrupt register in

R3328 to R3333, a corresponding mask

bit (IM_*) is provided in R3336 to R3341.

The mask bits are coded as:

0 = Do not mask interrupt

1 = Mask interrupt

Note

: The BOOT_DONE_EINT1 interrupt is ‘0’ (un-masked) by default; all

other interrupts are ‘1’ (masked) by default.

R3343

(0D0Fh)

Interrupt

Control

IM_IRQ1

IRQ1 Output Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

R3409

(0D51h)

AOD IRQ1

MICD_CLAMP_F

ALL_EINT1

MICDET Clamp Interrupt

(Falling edge triggered)

Note: Cleared when a ‘1’ is written.

MICD_CLAMP_R

ISE_EINT1

MICDET Clamp Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

GP5_FALL_EINT

GP5 Interrupt

(Falling edge triggered)

Note: Cleared when a ‘1’ is written.

GP5_RISE_EINT

GP5 Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

JD1_FALL_EINT

JD1 Interrupt

(Falling edge triggered)

Note: Cleared when a ‘1’ is written.

JD1_RISE_EINT

JD1 Interrupt

(Rising edge triggered)

Note: Cleared when a ‘1’ is written.

R3411

(0D53h)

AOD IRQ

Mask IRQ1

IM_*

For each *_EINT1 interrupt register in

R3409, a corresponding mask bit (IM_*)

is provided in R3411.

The mask bits are coded as:

0 = Do not mask interrupt

1 = Mask interrupt

Table 96 Interrupt 1 Control Registers

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