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WM8281ECS/R Scheda tecnica(PDF) 256 Page - Cirrus Logic

Il numero della parte WM8281ECS/R
Spiegazioni elettronici  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 256 Page - Cirrus Logic

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WM8281
256
Rev 4.0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
5
GP5_FALL_EINT
2
0
GP5 Interrupt
(Falling edge triggered)
Note: Cleared when a
‘1’ is written.
4
GP5_RISE_EINT
2
0
GP5 Interrupt
(Rising edge triggered)
Note: Cleared when a ‘1’ is written.
3
JD1_FALL_EINT
2
0
JD1 Interrupt
(Falling edge triggered)
Note: Cleared when a ‘1’ is written.
2
JD1_RISE_EINT
2
0
JD1 Interrupt
(Rising edge triggered)
Note: Cleared when a ‘1’ is written.
R3412
(0D54h)
AOD IRQ
Mask IRQ2
IM_*
1
For each *_EINT2 interrupt register in
R3410, a corresponding mask bit (IM_*)
is provided in R3412.
The mask bits are coded as:
0 = Do not mask interrupt
1 = Mask interrupt
Table 97 Interrupt 2 Control Registers
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3360
(0D20h)
Interrupt
Raw Status
1
11
DSP4_RAM_RD
Y_STS
0
DSP4 RAM Status
0 = Not ready
1 = Ready
10
DSP3_RAM_RD
Y_STS
0
DSP3 RAM Status
0 = Not ready
1 = Ready
9
DSP2_RAM_RD
Y_STS
0
DSP2 RAM Status
0 = Not ready
1 = Ready
8
DSP1_RAM_RD
Y_STS
0
DSP1 RAM Status
0 = Not ready
1 = Ready
7
DSP_IRQ8_STS
0
DSP IRQ8 Status
0 = Not asserted
1 = Asserted
6
DSP_IRQ7_STS
0
DSP IRQ7 Status
0 = Not asserted
1 = Asserted
5
DSP_IRQ6_STS
0
DSP IRQ6 Status
0 = Not asserted
1 = Asserted
4
DSP_IRQ5_STS
0
DSP IRQ5 Status
0 = Not asserted
1 = Asserted
3
DSP_IRQ4_STS
0
DSP IRQ4 Status
0 = Not asserted
1 = Asserted
2
DSP_IRQ3_STS
0
DSP IRQ3 Status
0 = Not asserted
1 = Asserted
1
DSP_IRQ2_STS
0
DSP IRQ2 Status
0 = Not asserted
1 = Asserted



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