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WM8281ECS/R Scheda tecnica(PDF) 259 Page - Cirrus Logic |
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WM8281ECS/R Scheda tecnica(HTML) 259 Page - Cirrus Logic |
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259 / 392 page ![]() WM8281 Rev 4.0 259 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Interrupt Raw Status 5 12 FX_CORE_OVE RCLOCKED_ST S 0 The bits are coded as: 0 = Normal 1 = Overclocked The OVERCLOCKED_STS bit will be asserted whenever any of these register bits is asserted. 10 DAC_SYS_OVE RCLOCKED_ST S 0 9 DAC_WARP_OV ERCLOCKED_S TS 0 8 ADC_OVERCLO CKED_STS 0 7 MIXER_OVERCL OCKED_STS 0 6 AIF3_ASYNC_O VERCLOCKED_ STS 0 5 AIF2_ASYNC_O VERCLOCKED_ STS 0 4 AIF1_ASYNC_O VERCLOCKED_ STS 0 3 AIF3_SYNC_OV ERCLOCKED_S TS 0 2 AIF2_SYNC_OV ERCLOCKED_S TS 0 1 AIF1_SYNC_OV ERCLOCKED_S TS 0 0 PAD_CTRL_OVE RCLOCKED_ST S 0 R3365 (0D25h) Interrupt Raw Status 6 15 SLIMBUS_SUBS YS_OVERCLOC KED_STS 0 Indicates an Overclocked Error condition for each respective sub-system. The bits are coded as: 0 = Normal 1 = Overclocked The OVERCLOCKED_STS bit will be asserted whenever any of these register bits is asserted. 14 SLIMBUS_ASYN C_OVERCLOCK ED_STS 0 13 SLIMBUS_SYNC _OVERCLOCKE D_STS 0 12 ASRC_ASYNC_S YS_OVERCLOC KED_STS 0 11 ASRC_ASYNC_ WARP_OVERCL OCKED_STS 0 10 ASRC_SYNC_SY S_OVERCLOCK ED_STS 0 9 ASRC_SYNC_W ARP_OVERCLO CKED_STS 0 8 DSP4_OVERCL OCKED_STS 0 7 DSP3_OVERCL OCKED_STS 0 |
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