WM8281ECSSLASHR datasheet(264/392 Pages) CIRRUS

264 / 392 page

WM8281

264

Rev 4.0

There are some restrictions to be observed regarding the automatic sample rate detection, as noted

below:



The

same

sample

rate

must

not

selected

than

one

the

SAMPLE_RATE_DETECT_n registers.



Sample rates 192kHz and 176.4kHz must not be selected concurrently.



Sample rates 96kHz and 88.2kHz must not be selected concurrently.

The control registers associated with the automatic sample rate detection function are described in

Table 101.

SYSCLK AND ASYNCCLK CONTROL

The SYSCLK and ASYNCCLK clocks may be provided directly from external inputs (MCLK, or slave

mode BCLK inputs). Alternatively, the SYSCLK and ASYNCCLK clocks can be derived using the

integrated FLL(s), with MCLK, BCLK, LRCLK or SLIMCLK as a reference.

The required SYSCLK frequency is dependent on the SAMPLE_RATE_n registers. Table 99

illustrates the valid SYSCLK frequencies for every supported sample rate.

The SYSCLK_FREQ and SYSCLK_FRAC registers are used to identify the applicable SYSCLK

frequency. It is recommended that the highest possible SYSCLK frequency is selected.

The chosen SYSCLK frequency must be valid for all of the SAMPLE_RATE_n registers. It follows that

all of the SAMPLE_RATE_n registers must select numerically-related values, ie. all from the same cell

as represented in Table 99.

Sample Rate

SAMPLE_RATE_

SYSCLK

Frequency

SYSCLK_FREQ

SYSCLK_FRAC

12kHz

24kHz

48kHz

96kHz

192kHz

4kHz

8kHz

16kHz

32kHz

01h

02h

03h

04h

05h

10h

11h

12h

13h

6.144MHz,

12.288MHz,

24.576MHz,

49.152MHz,

73.728MHz,

98.304MHz,

147.456MHz

000,

001,

010,

011,

100,

101,

110

11.025kHz

22.05kHz

44.1kHz

88.2kHz

176.4kHz

09h

0Ah

0Bh

0Ch

0Dh

5.6448MHz,

11.2896MHz,

22.5792MHz,

45.1584MHz,

67.7376MHz,

90.3168MHz,

135.4752MHz

000,

001,

010,

011,

100,

101,

110

Note that each of the SAMPLE_RATE_n registers must select a sample rate value from the same

group in the two lists above.

Table 99 SYSCLK Frequency Selection

The required ASYNCCLK frequency is dependent on the ASYNC_SAMPLE_RATE_n registers. Table

100 illustrates the valid ASYNCCLK frequencies for every supported sample rate.

The ASYNC_CLK_FREQ register is used to identify the applicable ASYNCCLK frequency. It is

recommended that the highest possible ASYNCCLK frequency is selected.

Note that, if all the sample rates in the system are synchronised to SYSCLK, then the ASYNCCLK

may not be required at all. In this case, the ASYNCCLK should be disabled (see Table 101), and the

associated register values are not important.

WM8281ECS/R Scheda tecnica(PDF) 264 Page - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 264 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL