WM8281ECSSLASHR datasheet(265/392 Pages) CIRRUS

265 / 392 page

WM8281

Rev 4.0

265

Sample Rate

ASYNC_SAMPLE_RATE_n

ASYNCCLK

Frequency

ASYNC_CLK_FREQ

12kHz

24kHz

48kHz

96kHz

192kHz

4kHz

8kHz

16kHz

32kHz

01h

02h

03h

04h

05h

10h

11h

12h

13h

6.144MHz,

12.288MHz,

24.576MHz,

49.152MHz

000,

001,

010,

011

11.025kHz

22.05kHz

44.1kHz

88.2kHz

176.4kHz

09h

0Ah

0Bh

0Ch

0Dh

5.6448MHz,

11.2896MHz,

22.5792MHz

45.1584MHz

000,

001,

010,

011

Note that each of the ASYNC_SAMPLE_RATE_n registers must select a sample rate value from

the same group in the two lists above.

Table 100 ASYNCCLK Frequency Selection

The WM8281 supports automatic clocking configuration. The programmable dividers associated with

the ADCs, DACs and all DSP functions are configured automatically, with values determined from the

SYSCLK_FREQ, SAMPLE_RATE_n, ASYNC_CLK_FREQ and ASYNC_SAMPLE_RATE_n fields.

Note that the digital audio interface (AIF) clocking rates must be configured separately.

The sample rates of each AIF, the input (ADC) paths, output (DAC) paths and DSP functions are

selected as described in the respective sections. Stereo full-duplex sample rate conversion is

supported in multiple configurations to allow digital audio to be routed between interfaces and for

asynchronous audio data to be mixed. See “Digital Core” for further details.

The SYSCLK_SRC register is used to select the SYSCLK source, as described in Table 101. The

source may be MCLKn, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is

selected as the source, then the relevant FLL must be enabled and configured, as described later.

The SYSCLK_FREQ and SYSCLK_FRAC registers are set according to the frequency of the selected

SYSCLK source.

The SYSCLK-referenced circuits within the digital core are clocked at a dynamically-controlled rate,

limited by the SYSCLK frequency itself. For maximum signal mixing and processing capacity, it is

recommended that the highest possible SYSCLK frequency is configured.

The SAMPLE_RATE_n registers are set according to the sample rate(s) that are required by one or

more of the WM8281 audio interfaces. The WM8281 supports sample rates ranging from 4kHz to

192kHz.

The SYSCLK signal is enabled by the register bit SYSCLK_ENA. The applicable clock source

(MCLKn, AIFnBCLK or FLLn) must be enabled before setting SYSCLK_ENA=1. This bit should be set

to 0 when reconfiguring the clock sources (see below for additional requirements when setting

SYSCLK_ENA=0).

When disabling SYSCLK, note that all of the input, output or digital core functions associated with the

SYSCLK clock domain must be disabled before setting SYSCLK_ENA=0.

When ‘0’ is written to SYSCLK_ENA, the host processor must wait until the WM8281 has shut down

the associated functions before issuing any other register write commands. The SYSCLK Enable

status can be polled via the SYSCLK_ENA_LOW_STS bit (see Table 98), or else monitored using the

Interrupt or GPIO functions.

The SYSCLK Enable status is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event -

see “Interrupts”. The corresponding Interrupt event indicates that the WM8281 has

shut down the SYSCLK functions and is ready to accept register write commands.

The SYSCLK Enable status can be output directly on a GPIO pin as an external indication of the

SYSCLK status. See “General Purpose Input / Output” to configure a GPIO pin for this function.

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