| Motore di ricerca datesheet componenti elettronici |
|
WM8281ECS/R Scheda tecnica(PDF) 277 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8281ECS/R Scheda tecnica(HTML) 277 Page - Cirrus Logic |
|
277 / 392 page ![]() WM8281 Rev 4.0 277 The FLL output frequency is generated according to the following equation: FOUT = (FVCO / FLLn_OUTDIV) The FLL operating frequency, FVCO is set according to the following equation: FVCO = (FREF x 3 x N.K x FLLn_FRATIO) FREF is the input frequency, as determined by FLLn_REFCLK_DIV. When the FLL output is selected as the SYSCLK or ASYNCCLK source, then FVCO must be exactly 294.912MHz (for 48kHz-related sample rates) or 270.9504MHz (for 44.1kHz-related sample rates). Note that the output frequencies that do not lie on or between the frequencies quoted above cannot be guaranteed across the full range of device operating conditions. In order to follow the above requirements for FVCO, the value of FLLn_OUTDIV should be selected according to the desired output FOUT. The divider, FLLn_OUTDIV, must be set so that FVCO is in the range 270MHz to 295MHz. The available divisions are integers from 2 to 7. Some typical settings of FLLn_OUTDIV are noted in Table 102. OUTPUT FREQUENCY FOUT FLLn_OUTDIV 45 MHz to 52 MHz 110 (divide by 6) 67.5 MHz to 78 MHz 100 (divide by 4) 90 MHz to 104 MHz 011 (divide by 3) 135 MHz to 150 MHz 010 (divide by 2) Table 102 Selection of FLLn_OUTDIV The FLLn_FRATIO field selects the frequency division ratio of the FLL input. The FLLn_GAIN field is used to optimise the FLL, according to the input frequency. As a general guide, these fields should be selected as described in Table 103. (Note that additional guidelines also apply, as described below.) REFERENCE FREQUENCY FREF FLLn_FRATIO FLLn_GAIN 1MHz - 13.5MHz 0h (divide by 1) 4h (16x gain) 256kHz - 1MHz 1h (divide by 2) 2h (4x gain) 128kHz - 256kHz 3h (divide by 4) 0h (1x gain) 64kHz - 128kHz 7h (divide by 8) 0h (1x gain) Less than 64kHz Fh (divide by 16) 0h (1x gain) Table 103 Selection of FLLn_FRATIO and FLLn_GAIN In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be calculated, as given by the following equation: FVCO = (FOUT x FLLn_OUTDIV) The value of N.K can then be determined as follows: N.K = FVCO / (FLLn_FRATIO x 3 x FREF) Note that, in the above equations: FLLn_OUTDIV is the FOUT clock ratio. FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable. FLLn_FRATIO is the FVCO clock ratio (1, 2, 3 … 16). |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |