WM8281ECSSLASHR datasheet(280/392 Pages) CIRRUS

280 / 392 page

WM8281

280

Rev 4.0

The FLL control registers are described in Table 106 and Table 107. Example settings for a variety of

reference frequencies and output frequencies are shown in Table 110.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R369

(0171h)

FLL1

Control 1

FLL1_ENA

FLL1 Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the

FLL1 enable sequence, ie. after the other

FLL registers have been configured.

R370

(0172h)

FLL1

Control 2

FLL1_CTRL_UP

FLL1 Control Update

Write ‘1’ to apply the FLL1_N and

FLL1_THETA register settings.

(Only valid when FLL1_ENA=1)

9:0

FLL1_N [9:0]

008h

FLL1 Integer multiply for FREF

(LSB = 1)

If updated while the FLL is enabled, the

new value is only effective

when a ‘1’ is

written to FLL1_CTRL_UPD.

R371

(0173h)

FLL1

Control 3

15:0

FLL1_THETA

[15:0]

0018h

FLL1 Fractional multiply for FREF

This field sets the numerator (multiply)

part of the FLL1_THETA / FLL1_LAMBDA

ratio.

Coded as LSB = 1.

If updated while the FLL is enabled, the

new value is only effective

when a ‘1’ is

written to FLL1_CTRL_UPD.

R372

(0174h)

FLL1

Control 4

15:0

FLL1_LAMBDA

[15:0]

007Dh

FLL1 Fractional multiply for FREF

This field sets the denominator (dividing)

part of the FLL1_THETA / FLL1_LAMBDA

ratio.

Coded as LSB = 1.

R373

(0175h)

FLL1

Control 5

11:8

FLL1_FRATIO

[3:0]

FLL1 FVCO clock divider

0h = 1

1h = 2

2h = 3

3h = 4

…

Fh = 16

3:1

FLL1_OUTDIV

[2:0]

011

FLL1 FOUT clock divider

000 = Reserved

001 = Reserved

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5

110 = Divide by 6

111 = Divide by 7

(FOUT = FVCO / FLL1_OUTDIV)

R374

(0176h)

FLL1

Control 6

7:6

FLL1_REFCLK_

DIV [1:0]

FLL1 Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be

divided down to <=13.5MHz.

For lower power operation, the reference

clock can be divided down further if

desired.

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