AD9546SLASHPCBZ datasheet(24/205 Pages) AD

24 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 24 of 205

DPLL PROPAGATION DELAY VARIATION

The PLL channels of the AD9546 have an inherent propagation delay (see Table 18) that can be nominally offset using the skew

adjustment feature in the source profiles of the device. Dynamic variations that are proportional to temperature change can be mitigated

with the delay compensation mechanism of the AD9546.

A polynomial with programmable coefficients of temperature (see the Delay Compensation section) determines the response of the delay

compensation circuit. An additive inverse of the polynomial function derives from a best fit algorithm applied to the uncompensated

delay variation measurements. Active delay compensation uses the additive inverse polynomial in an attempt to nullify the delay

variation over temperature. For a second-order polynomial, the measured data without delay compensation in Table 19 is the first-order

representation for the various device configurations. A repeat of the same measurement with the inverse coefficient programmed yields

the slopes of the residual delay in the specifications with delay compensation in Table 19. See Figure 25 and Figure 26 for the related

plots.

The tabulated data with delay compensation in Table 19 reflects an average of several devices that are programmed with the same delay

compensation coefficients. The tabulated residual errors are greater than expected for coefficients that are optimized for an individual

device.

The DPLL propagation delay variation results depend on the device being configured with a 1:1 frequency translation ratio, where fREF =

fOUT = 10 MHz, the reference input configured to 1.2V CMOS, and DPLL configured to zero delay (hitless). A die temperature range of

−40°C to +105°C applies for both the uncompensated and compensated results.

Table 19.

Parameter

Min

Typ

Max

Unit

OUTPUT DRIVER MODE

Differential

CML

Without Delay Compensation

0.517

ps/°C

With Delay Compensation

−0.0155

ps/°C

HCSL

Without Delay Compensation

0.624

ps/°C

With Delay Compensation

−0.0253

ps/°C

Single-Ended

CML

Without Delay Compensation

0.681

ps/°C

With Delay Compensation

0.0208

ps/°C

HCSL

Without Delay Compensation

0.861

ps/°C

With Delay Compensation

0.0288

ps/°C

AD9546/PCBZ Scheda tecnica(PDF) 24 Page - Analog Devices

AD9546/PCBZ Scheda tecnica(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL