AD9546SLASHPCBZ datasheet(3/205 Pages) AD

3 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 3 of 205

Adding Time Offset to the Synchronization Time ................62

Synchronization Offset Refinement.........................................62

Maximum Magnitude Detection..............................................62

Latency Detection .......................................................................62

Synchronization Slew Limiter...................................................63

Restart...........................................................................................63

Synchronization Guard..............................................................63

Initial Synchronization...............................................................64

Ready Status.................................................................................64

User Time Stamper (UTS).............................................................65

Overview ......................................................................................65

UTS Channel Control Registers Addresses.............................65

UTS Channel Enable ..................................................................65

UTS Channel Time Stamp Source............................................66

UTS Channel Time Offset .........................................................66

UTS Channel Tag........................................................................66

UTS Channel Time Format.......................................................66

UTS Channel Status Flag Assignment .....................................66

UTS Readback FIFO...................................................................67

Inverse User Time Stamper (IUTS)..............................................69

Overview ......................................................................................69

Parameter Destination Selection ..............................................70

Time Code and Format..............................................................70

IUTS Time Offset........................................................................70

IUTS Status ..................................................................................70

IUTS Restart ................................................................................70

IUTS Bypass Lock Option .........................................................70

Declaring an IUTS Invalid.........................................................70

Analog Clock Loopback.................................................................71

Overview ......................................................................................71

Analog Loopback Feature..........................................................72

Measuring Round Trip Delay ...................................................72

Excessive Round Trip Delay......................................................73

System Clock PLL ...........................................................................74

System Clock PLL Overview .....................................................74

System Clock Input Frequency Declaration ...........................74

System Clock Source ..................................................................74

Prescale Divider...........................................................................75

Feedback Divider ........................................................................75

System Clock PLL Output Frequency......................................75

System Clock PLL Lock Detector .............................................75

System Clock Stability Timer....................................................75

System Clock Calibration ..........................................................75

System Clock Stability Compensation.....................................76

Reference Clock Input Resources.................................................77

Reference Receivers ........................................................................78

Reference Receivers Overview ..................................................78

Single-Ended Mode ....................................................................78

Differential Mode .......................................................................79

Reference Dividers (R Dividers)...................................................80

Reference Monitor..........................................................................81

Reference Monitor Overview....................................................81

Reference Monitor Base Period ................................................82

Reference Monitor Status Indicators .......................................82

Reference Monitor Controls .....................................................82

Discontinuity Detection.............................................................85

Reference Period Jitter Estimation...........................................85

Reference Monitor Decision Time...........................................85

Reference Validation..................................................................85

Reference Monitor Reset ...........................................................86

Reference Demodulator .................................................................87

Reference Demodulator Overview...........................................87

Interaction Between Demodulator and Reference Monitor.87

Modulated Cycles and Modulation Events.............................88

Balanced and Unbalanced Modulation ...................................88

Enabling a Demodulator............................................................88

Modulation Polarity Detection.................................................88

Demodulator Sensitivity ............................................................89

Demodulator Persistence...........................................................89

Demodulator Bandwidth...........................................................89

Demodulator Synchronization .................................................90

Distribution Clock Output Drivers..............................................91

Distribution Clock Output Drivers Overview........................91

Output Current Control ............................................................91

Output Mode Control................................................................91

Output Driver Configurations..................................................92

Output Driver Reset ...................................................................93

Output Muting............................................................................93

Distribution Dividers (Q Dividers)..............................................94

Distribution Dividers Overview ...............................................94

Q Divider Clock Source Selection ............................................95

Integer Division ..........................................................................95

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