AD9546SLASHPCBZ datasheet(62/205 Pages) AD

62 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 62 of 205

ADDING TIME SKEW TO THE SYNCHRONIZATION

TIME

In a digitized clocking system with redundant common clock

references, a time skew specific to each reference path may

exist. The user can compensate the skew by programming the

appropriate time skew for each path.

The skew programs as a 24-bit signed value. Primary skew is via

The 24-bit programmed time skew is in units of 2−48 sec,

yielding a range of approximately ±29.8 ns. For example, to

program a time skew of −5 ns (−5 × 10−9 sec), first convert to

the appropriate units and round the result to the nearest integer

as follows:

−5 × 10−9 × 248 = −1,407,375

This resulting value in 24-bit hexadecimal format is: 0x EA 8671.

ADDING TIME OFFSET TO THE

SYNCHRONIZATION TIME

In a digitized clocking system with redundant common clock

references, a time skew common to both reference paths may

exist. The user can compensate for the common time skew by

programming the appropriate time offset value.

The time offset programs as a 32-bit signed value in

a range of approximately ±15.26 μs. For example, to program a

time skew of 50 ns (50 × 10−9 sec), first convert to the appropriate

units and round the result to the nearest integer as follows:

50 × 10−9 × 248 = 14,073,749

This value in 32-bit hexadecimal format is: 0x 00D6 BF95.

SYNCHRONIZATION OFFSET REFINEMENT

In a digitized clocking application, the common clock

synchronization process is typically iterative (though not a

strict requirement). That is, the user applies a continuous

synchronization source and continuously writes

synchronization time values for each expected synchronization

event. As such, each synchronization and time pair results in a

specific synchronization offset value. However, a series of

synchronization offset values is likely to introduce jitter onto

the common time scale.

As such, the CCS employs a synchronization offset refinement

block that gradually softens the impact of each new

synchronization offset value. The goal is to yield an average

synchronization offset over time. That is, the synchronization

offset value produced by the first synchronization event

(following a restart condition) propagates through the

refinement block unaltered. As synchronization events

continue to occur, the synchronization offset refinement block

applies progressively more filtering (up to a limit) to

subsequent synchronization offset values.

The user can restart the synchronization offset refinement at

any time (see the Restart section).

MAXIMUM MAGNITUDE DETECTION

The CCS provides the user with the option to prevent excessive

synchronization offset values from propagating into the

synchronization offset refinement process. The user activates

the maximum magnitude detection block by programming a

nonzero guard adjustment value in Register 0x0D39 to Register

0x0D3B. A zero value (default) disables the maximum

magnitude detection feature.

When activated, the maximum magnitude detector monitors

each new synchronization offset value and compares it to the

guard adjustment value. If a synchronization offset value

exceeds the guard adjustment value, the maximum magnitude

detector signals a guard event (see the Synchronization Guard

section), thereby preventing the offending synchronization

offset value from propagating into the synchronization offset

refinement process.

The maximum magnitude detector ignores the first

synchronization event following a restart or after the initial

synchronization block indicates initial synchronization (see the

Initial Synchronization section).

The guard adjustment value comprises a 20-bit unsigned

number in units of 2−40 sec (~0.91 ps), yielding a maximum

guard value of up to 954 ns (approximately). For example, to

set the maximum magnitude detection value to 10 ns, first

convert to the appropriate units and round the result to the

nearest integer as follows:

10 × 10−9 × 240 = 10,995

This value in 20-bit hexadecimal format is: 0x 0 2AF3.

LATENCY DETECTION

The normal synchronization process involves the occurrence of

a synchronization event followed by the application of the

synchronization time associated with the synchronization

event. When a synchronization event occurs, the common

clock synchronizer waits for the user to issue a synchronization

time value associated with the synchronization event. The

purpose of the latency detector is to allow the user to apply a

time limit on how long the CCS waits for a synchronization time

value before discarding the synchronization event. If a

synchronization time value does not arrive within the specified

period, the latency detector signals a guard event (see the

Synchronization Guard section).

The user activates latency detection by writing a nonzero value to

the 16-bit unsigned guard latency bit field in Register 0x0D37

to Register 0x0D38 in units of 2−16 sec, yielding a maximum

latency guard time of slightly less than 1 sec. A zero value

(default) disables the latency guard feature.

AD9546/PCBZ Scheda tecnica(PDF) 62 Page - Analog Devices

AD9546/PCBZ Scheda tecnica(HTML) 62 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL