AD9546SLASHPCBZ datasheet(58/205 Pages) AD

58 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 58 of 205

COMMON CLOCK REFERENCE SWITCHOVER

The CCDPLL uses an integrated controller to handle the

activation and deactivation of the loop based on the status of

the CCRs. Because the CCDPLL supports redundant CCRs, the

controller requires a priority scheme to handle transitions from

one CCR to another.

The controller gives nonrevertive priority to CCR0, meaning

that after the controller activates the loop using a specific CCR,

the controller continues using that CCR until the CCR

invalidates. If both CCRs are operational at power-up, however,

there is the risk that CCR1 may validate before CCR0, causing

CCR1 to be the active reference, which is contrary to the

desired nonrevertive priority assigned to CCR0. The controller

solves this potential problem by adding a validation delay to the

validation of CCR1. The delay ensures nonrevertive priority to

CCR0, but the delay is only in effect when CCR0 is invalid (the

delay is unnecessary otherwise).

The user can determine which reference is currently active via

Bit 3 of Register 0x0D40. Logic 0 or Logic 1 indicates CCR0 or

CCR1 is active, respectively. Bit 3 is undefined for legacy

auxiliary DPLL operation.

ACTIVE STATUS

The CCDPLL provides a status bit that indicates the CCDPLL

is actively tracking a reference input signal. To check the active

status of the CCDPLL, use Bit 0 of Register 0x0D40, where

Logic 1 indicates the common clock DPLL is active.

AD9546/PCBZ Scheda tecnica(PDF) 58 Page - Analog Devices