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AD9546/PCBZ Scheda tecnica(PDF) 73 Page - Analog Devices |
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AD9546/PCBZ Scheda tecnica(HTML) 73 Page - Analog Devices |
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73 / 205 page ![]() Data Sheet AD9546 Rev. 0 | Page 73 of 205 EMBEDDED CLOCK DEMODULATOR REFB REFBB DIFFERENTIAL SINGLE- ENDED TIME STAMPS TDC TDC SYNC M4 Mx PIN FUNCTION LOGIC 1-OF-6 LOOPBACK PATH SELECTOR A B C 3 SYNC REG 0x2D02, BITS[2:0] SINGLE- ENDED EMBEDDED CLOCK DEMODULATOR ÷R ÷R TIME STAMPS NOTES 1. A RANGE OF BITS USES A COLON SEPARATOR REG 0x0106, BIT 7 = 1 Figure 56. Analog Loopback Detail The TC1 and TC2 time codes occur sequentially in pairs: TC1[x] and TC2[x], TC1[x + 1] and TC2[x + 1], and so on. Each time code pair provides a round trip delay measurement, RTD, given by RTD[x] = TC2[x] − TC1[x] Ideally, each RTD[x] is the same value, but in practice, the RTD[x] values vary slightly due to various noise contributors. Generally, the user takes an average of several RTD[x] values to yield an improved estimate of round trip delay. The round trip delay measurement includes all delays in the loopback path: interconnections and active elements (like buffers and other semiconductor components). However, Table 29 provides static delay values for sections of the internal loopback paths, which the user can subtract from the round trip delay measurement to account for the delay associated with the internal paths of the device. The resulting value, RTDCORR, constitutes the corrected round trip delay, which consists of the total interconnect delay (forward and reverse paths) along with delay contributions of any other components in the path. The small error due to the difference between the mean specified component delays and the actual component delays also exists. Assuming the interconnect delay dominates, an approximation of the forward (or reverse) path interconnect delay, Δt, is Δt = ½ × RTDCORR With a value for RTDCORR and knowledge of the mean component delays in the signal path, the user can program corrective offsets in the appropriate nodes to counteract the path delay. EXCESSIVE ROUND TRIP DELAY In some applications, interconnect lengths may result in a round trip delay that exceeds the period of the underlying clock period. Such a situation breaks the symmetry of the TC1 and TC2 time code pairs. Techniques exist to overcome excessive round trip delay, but such is beyond the scope of this data sheet. |
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