AD9546SLASHPCBZ datasheet(2/205 Pages) AD

2 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 2 of 205

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications ...................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 5

Functional Block Diagram .............................................................. 6

Specifications .................................................................................... 7

Operating Temperature............................................................... 7

Supply Voltage.............................................................................. 7

Supply Current ............................................................................. 7

Power Dissipation ........................................................................ 8

System Clock Inputs, XOA and XOB........................................ 9

Reference Inputs......................................................................... 10

Reference to Reference Coupling............................................. 12

REFx to REFx Input Timing Skew........................................... 14

REFx to Auxiliary REFx Input Timing Skew ......................... 15

Reference Monitors.................................................................... 16

Distribution Clock Outputs...................................................... 17

Output to Output Timing Skew............................................... 19

Output Timing Skew Between Mx Pins and OUTxyP and/or

OUTxyN Pins ............................................................................. 20

Time Duration of Digital Functions........................................ 20

DPLL0 and DPLL1 Specifications............................................ 21

DPLL Lock Detection Specifications....................................... 21

DPLL Phase Characteristics...................................................... 22

DPLL Propagation Delay .......................................................... 23

DPLL Propagation Delay Variation ........................................ 24

Holdover Specifications............................................................. 25

Analog PLL (APLL0 and APLL1) Specifications................... 25

Output Channel Divider Specifications.................................. 25

Time to Digital Converter (TDC) Specifications .................. 26

Auxiliary NCO Specifications .................................................. 26

Common Clock DPLL Specifications...................................... 26

Common Clock Synchronizer (CCS) Specifications ............ 27

User Time Stampers (UTS) Specifications ............................. 27

Inverse User Time Stampers (IUTS) Specifications.............. 28

Analog Loopback (Round Trip Delay) Specifications .......... 29

Mx to Mx Pin Output Timing Skew........................................ 30

System Clock Compensation Specifications .......................... 30

Temperature Sensor Specifications ......................................... 30

Logic Input Specifications (RESETB, M0 to CSB/M6 Pins) 30

Logic Output Specifications (M0 to CSB/M6 Pins) .............. 31

Serial Port Specifications........................................................... 32

Jitter Generation (Random Jitter)............................................ 34

Phase Noise ................................................................................. 35

Absolute Maximum Ratings......................................................... 38

Thermal Resistance.................................................................... 38

ESD Caution ............................................................................... 38

Pin Configuration and Function Descriptions .......................... 39

Typical Performance Characteristics .......................................... 42

Terminology.................................................................................... 47

Theory of Operation ...................................................................... 48

Input/Output Termination Recommendations......................... 49

System Clock Inputs .................................................................. 49

Reference Clock Inputs ............................................................. 49

Clock Outputs............................................................................. 50

Digitized Clocking.......................................................................... 52

Overview...................................................................................... 52

System Clock PLL Component ................................................ 52

Common Clock DPLL Component ........................................ 52

Physical Clock Converter.......................................................... 52

Physical Clock Generator.......................................................... 52

Common Clock Synchronizer Component ........................... 54

User Time Stamper (UTS) and Inverse User Timer Stamper

(IUTS) Components.................................................................. 54

A Digitized Clocking Node Example ...................................... 54

Common Clock DPLL (CCDPLL)............................................... 56

Overview...................................................................................... 56

Common Clock References ...................................................... 56

Common Clock Reference Monitor........................................ 57

CCDPLL Lock Detector ............................................................ 57

CCDPLL Loop Filter.................................................................. 57

Common Clock Reference (CCR) Period Declaration......... 57

Common Clock Reference Switchover ................................... 58

Active Status................................................................................ 58

Common Clock Synchronizer (CCS).......................................... 59

Overview...................................................................................... 59

Synchronization Source ............................................................ 60

Tagged Synchronization ........................................................... 60

Synchronization Time............................................................... 61

Adding Time Skew to the Synchronization Time................. 62

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