AD9546SLASHPCBZ datasheet(88/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 88 of 205

MODULATED CYCLES AND MODULATION EVENTS

The reference demodulator detects the arrival of modulated

carrier cycles. A modulated cycle spans one period of the input

reference clock (tCARRIER) and consists of a predefined phase

deviation relative to the expected falling edge of the input clock.

The definition of a modulated cycle is when the duration of the

second half of a carrier cycle is lengthened or shortened by

some period of time, Δt (see Figure 63). In general, Δt is

constant for a given application and defines the modulation

depth, where the magnitude of the modulation depth is always

less than ½.

CARRIER

Modulation Depth

∆

The reference demodulator uses two modulated cycles to

identify a modulation event, although the second modulated

cycle can be unmodulated in the case of unbalanced

modulation (see Figure 63).

The demodulator performs no type of error detection on the

modulated carrier cycles.

BALANCED AND UNBALANCED MODULATION

The demodulator recognizes two types of modulation events:

unbalanced and balanced. Figure 63 shows generalized

examples of the modulation event types and their polarity.

Unbalanced modulation occurs when the second modulated

cycle of a modulation event is unmodulated. Note that

unbalanced modulation only modulates the first modulated

cycle of a modulation event. Therefore, an unbalanced

modulation event shifts the dc offset of the carrier signal

(relative to an unmodulated carrier).

Balanced modulation occurs when the second modulated cycle

of a modulation event has the opposite polarity modulation of

the first modulation event. For example, when the first

modulation event has a period deviation of +Δt, then the

second modulation event must have a period of –Δt (or vice

versa). Because balanced modulation modulates the first and

second modulated cycles of a modulation event in opposite

fashion, balanced modulation events do not shift the dc balance

of the carrier signal.

The first modulated cycle in a modulation event determines the

polarity of the modulation event. A modulated cycle of –Δt

equates to Logic 0, whereas a modulated cycle of +Δt equates to

Logic 1.

ENABLING A DEMODULATOR

To enable a specific demodulator, use Bit 3 of Register M per

the register legend in Figure 62. Logic 0 (default) disables the

demodulator and holds it in a reset state. Logic 1 enables the

demodulator to detect modulation events.

MODULATION POLARITY DETECTION

When Bit 7 = 1 of Register M per the register legend in Figure 62,

the demodulator must automatically determine the polarity of

the first modulated cycle of a modulation event (see Figure 63).

However, the autodetect feature reduces the overall sensitivity

of the demodulator.

The reference demodulator is most sensitive when it is aware of

the modulation polarity in advance. The user can take

advantage of the maximum sensitivity of the demodulator by

programming Bit 2 in Register M per the register legend in

Figure 62 (assuming Bit 7 = 0 in Register M per the register

legend in Figure 62). The value of Bit 2 indicates the expected

polarity of Δt in the first modulated cycle of a modulation event

(see Figure 63). Logic 0 (default) indicates negative Δt, and

Logic 1 indicates positive Δt.

–Δt

MODULATION EVENT

MODULATED CYCLE

UNBALANCED

MODULATION

(LOGIC 1)

BALANCED

MODULATION

(LOGIC 0)

BALANCED

MODULATION

(LOGIC 1)

50%

DC SHIFT

UNMODULATED

CYCLE

NO DC

SHIFT

tCARRIER

UNBALANCED

MODULATION

(LOGIC 0)

50%

NO DC

SHIFT

DC SHIFT

+Δt

–Δt

+Δt

–Δt

tCARRIER

2 × tCARRIER

Figure 63. Modulation Events

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