AD9546SLASHPCBZ datasheet(71/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 71 of 205

ANALOG CLOCK LOOPBACK

OVERVIEW

Analog loopback provides a means for designers of distributed

clock systems to loop an analog clock signal back to measure

the round trip delay. Knowledge of the round trip delay allows

the user to estimate the timing error associated with physical

connections (cables and circuit board traces, for example) and

compensate for those errors in downstream nodes. The net

effect is improved synchronization between nodes in a

distributed clock system.

The diagram of Figure 55 shows an example of a distributed

digitized clocking system comprising three AD9546 devices.

On the left is the master timing node, and on the right are the

slave timing nodes. Each node has a processor with a SPI

connection to the AD9546 associated with the node and a

digital bus interconnection between the processors of all nodes.

The main purpose of the digital bus is the transport of digitized

clocks between nodes. However, the digital bus enables the

transport of other data between nodes, allowing node

processors to share data (for example, time offset information

for correcting delays between nodes).

The primary timing signal for the system is a common clock

reference, which drives the REFB input of the master node. The

master node generates its common time scale from the

common clock reference. The master node also uses the

common clock reference to generate common clock signals that

route to the slave nodes. The common clocks result from

routing the common clock reference through the master DPLL

channel, preferably operating in zero delay mode to minimize

phase (delay) offset. The slave nodes use the common clock to

generate their own common time scale and output clock

signals. The goal of the distributed clock system is to have all

output clock signals of the slave nodes synchronous to the

common clock of the slave node, which is synchronous to the

common clock reference of the master.

A significant challenge in the implementation of a high

precision distributed clock system is accounting for the time

delay of the common clock as it propagates to each slave node.

The delay arises from the physical interconnects (cables, for

example) as well as active components (drivers and buffers, for

example) in the signal path. Without knowledge of the amount

of delay associated with each master to slave common clock

path, the delay constitutes a timing error that degrades the

precision of synchronization between nodes. To help remedy

delay errors, the AD9546 offers high resolution time

measurement capability (the UTS system) together with an

analog loopback feature to provide a mechanism to quantify

timing errors in the signal path. By quantifying the time errors,

the user can compensate for those errors by inserting corrective

time offsets via the various offset controls provided by the

AD9546.

REFB

PHYSICAL

CLOCK

CONVERTER

UTS

COMMON CLOCK

DPLL AND

SYNCHRONIZER

DPLL

CHANNEL

UTS

PHYSICAL

CLOCK

CONVERTER

TIME

STAMPS

TIME

STAMPS

COMMON

TIME

SCALE

PROCESSOR

COMMON

CLOCK

REFERENCE

REFB

TIME

STAMPS

PROCESSOR

ANALOG

LOOPBACK ANALOG

CLOCK

SIGNALS

PROCESSOR

DIGITIZED CLOCK TRANSPORT

ANALOG

CLOCK

SIGNALS

MASTER

DIGITIZED

CLOCKING

NODE

SLAVE

DIGITIZED

CLOCKING

NODE

ZERO DELAY

OPERATING

MODE

COMMON

CLOCK

ANALOG

LOOPBACK

AD9546

PHYSICAL

CLOCK

CONVERTER

TS1

TS2

SPI

SLAVE

DIGITIZED

CLOCKING

NODE

TS3

TC3

TC1

TC2

PHYSICAL

CLOCK

CONVERTER

REFB

TIME

STAMPS

ANALOG

LOOPBACK

ANALOG

CLOCK

SIGNALS

AD9546

PHYSICAL

CLOCK

CONVERTER

SPI

NOTES

1. TS1 TO TS3 CONSTITUTE TIME STAMP SEQUENCE 1 TO TIME STAMP SEQUENCE 3.

2. TC1 TO TC3 CONSTITUTE TIME CODE SEQUENCE 1 TO TIME CODE SEQUENCE 3.

Figure 55. Distributed Clock System with Analog Loopback

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