AD9546SLASHPCBZ datasheet(57/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 57 of 205

COMMON CLOCK REFERENCE MONITOR

The reference monitor for CCR0 uses the reference monitor

hardware of the legacy auxiliary DPLL. Because the CCDPLL

supports reference redundancy, however, it requires a second

reference monitor for CCR1. Thus, the CCDPLL implements a

duplicate reference monitor for CCR1. The CCR1 reference

monitor includes a validation delay feature (see the Common

Clock Reference Switchover section).

Each CCR reference monitor continuously observes the post

R divider period (tCCR) of each CCR source, where tCCR = R × tREF

(see the Reference Monitor Controls section of the Reference

Monitor section for details on tREF). The reference monitor

considers a CCR valid when the period of the specified source

of the CCR is within ±3.125% of tCCR. Conversely, a CCR is

invalid when the CCR reference monitor fails to detect the next

rising edge event within two tCCR periods, or the user clears the

enable bit associated with the CCR.

Each CCR reference monitor provides a status bit to indicate

that the CCR is valid (Logic 1), via Bit 4 and Bit 5 of

of the CCR reference monitors (valid and invalid) are also part

of the IRQ mechanism (see Bits[7:4] of Register 0x301D and

the Interrupt Request (IRQ) section). The status bits (Bit 4 and

Bit 5 of Register 0x0D40) are undefined for legacy auxiliary

DPLL operation. Furthermore, when using the common clock

DPLL, the legacy auxiliary DPLL reference status bit (Bit 2 of

The CCDPLL uses the status of the CCR reference monitors to

coordinate automatic reference switchover as described in the

Common Clock Reference Switchover section.

CCDPLL LOCK DETECTOR

By default, the CCDPLL uses the same lock detector as the

legacy auxiliary DPLL (see the Auxiliary DPLL Reference

Monitor Status section of the System Clock Compensation

section). However, the auxiliary DPLL lock detector has fixed

parameters that are not adjustable by the user. Thus, the default

lock detector is not well suited to digitized clocking applications.

To resolve this issue, the CCDPLL has access to a specialized

lock detector with programmable features, the CCDPLL lock

detector. The general functionality of the CCDPLL lock

detector is identical to the phase lock detector employed in the

channel DPLLs (DPLL0 and DPLL1). Refer to the DPLL Phase

Lock Detector section of the Digital PLL (DPLL) section for

details.

The phase lock threshold, phase lock fill, and phase lock drain

parameters of the CCDPLL lock detector appear in different

registers than those associated with DPLL0 and DPLL1:

Furthermore, the common clock DPLL uses the legacy auxiliary

DPLL lock detector by default. To enable the CCDPLL lock

detector, the user must program a nonzero value for the phase

lock threshold parameter. Otherwise, the phase lock fill and

drain parameters have no function, because they are

meaningless in the context of the legacy auxiliary DPLL.

When the user enables the CCDPLL lock detector, a stability

timer becomes available for use. The stability timer allows the

user to specify a fixed delay for indicating a locked status after

the phase lock detector makes a transition from an unlocked to

a locked state. The time delay provides for a more robust

indication of lock, because it allows additional time for lock and

unlock chatter to resolve. The stability timer uses an unsigned

16-bit value (units of milliseconds) via Register 0x0D04 to

stability timer. Otherwise, the CCDPLL lock detector bypasses

the stability timer.

The user has access to the status of the CCDPLL lock detector

via Bit 1 of Register 0x0D40 or Bit 1 of Register 0x3002. Logic 1

indicates locked, and Logic 0 indicates unlocked.

CCDPLL LOOP FILTER

The CCDPLL loop filter and the auxiliary DPLL loop filter use

the same loop filter hardware. As such, the user can program

the bandwidth of the loop filter as described in the Auxiliary

DPLL Loop Bandwidth section of the System Clock

Compensation section.

COMMON CLOCK REFERENCE (CCR) PERIOD

DECLARATION

Because a CCR is a time stamp source, the user programs the

expected reference period, tREF, in the reference monitor

controls for a specific source (see the Reference Monitor

Controls section of the Reference Monitor section for details on

tREF). However, tREF is subject to rounding errors, which are

typically small enough to ignore.

Although tREF is sufficiently precise for use by the reference

monitors, it is generally not precise enough for use by the

CCDPLL. The reason is the CCDPLL generates a local time

scale based on integrating tREF. Integrating tREF, however, poses a

problem because even a minuscule error accumulates over

time. To remedy this problem, the CCDPLL provides a

mechanism for declaring the reference period rationally as a

numerator (NUM) and denominator (DEN).

For example, consider a 38.88 MHz reference frequency. The

period, in rational terms, is 1/38,880,000. For this case, the

numerator = 1 and the denominator = 38,880,000. The user

programs the numerator and denominator values in

The rational period functionality is inactive by default (that is,

denominator = 0), which means the common clock DPLL uses

tREF strictly as the period definition by default. As such, to make

use of the rational period functionality, the user must program

the denominator with a nonzero value.

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