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AD9546/PCBZ Scheda tecnica(PDF) 30 Page - Analog Devices |
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AD9546/PCBZ Scheda tecnica(HTML) 30 Page - Analog Devices |
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30 / 205 page  AD9546 Data Sheet Rev. 0 | Page 30 of 205 Mx TO Mx PIN OUTPUT TIMING SKEW The data in Table 30 indicates the time offset of the target Mx pin clock edge relative to the M0 pin clock edge. Table 30 indicates the difference in output timing between Mx pins that are configured as outputs. The M0 pin and target Mx pins use the same internal status source. To determine the skew between any two Mx pins (for example, M2 to SDO/M5), subtract the values in the appropriate rows (skew from M2 to SDO/M5 is 190 − 760 = −570 ps). Note that the supply voltage on VDDIOA and VDDIOB has minimal effect (when the nominal supply voltage of each is similar) on the output timing skew. Table 30. Parameter Min Typ Max Unit TIMING SKEW M0 to M1 160 ps M0 to M2 190 ps M0 to M3 630 ps M0 to M4 1250 ps M0 to SDO/M5 760 ps M0 to CSB/M6 150 ps SYSTEM CLOCK COMPENSATION SPECIFICATIONS Table 31. Parameter Min Typ Max Unit Test Conditions/Comments OPEN-LOOP COMPENSATION See the Compensation Method 1 section Resolution 0.028 ppt ppt is parts per trillion (10−12) CLOSED-LOOP COMPENSATION (AUXILIARY DPLL) See the Compensation Method 3 section Phase Detector Frequency 2 200 kHz Loop Bandwidth 0.1 2 × 103 Hz Reference Monitor Threshold 5 % TEMPERATURE SENSOR SPECIFICATIONS Table 32. Parameter Min Typ Max Unit Test Conditions/Comments TEMPERATURE Accuracy TA = −50°C to +110°C Absolute Die Temperature 5 °C Relative Die Temperature 1.7 % Resolution 0.0078 °C 16-bit (signed) resolution Conversion time 0.18 ms REPEATABILITY ±0.02 °C TA = 25°C DRIFT 0.1 °C 500-hour stress test at 100°C LOGIC INPUT SPECIFICATIONS (RESETB, M0 TO CSB/M6 PINS) Table 33. Parameter Min Typ Max Unit Test Conditions/Comments RESETB Valid for 3.3 V ≥ VDDIOA ≥ 1.8 V; internal 100 kΩ pull-up resistor Input Voltage High, VIH VDDIOA − 0.4 V Low, VIL 0.4 V Input Current High, IINH 1 µA Low, IINL ±15 ±125 µA |
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