AD9546SLASHPCBZ datasheet(81/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 81 of 205

REFERENCE MONITOR

REFERENCE MONITOR OVERVIEW

The AD9546 has eight independent reference monitors, one for

each reference input. Figure 60 shows the REFA input along

with its associated reference monitor. The reference monitor

diagram of Figure 60 applies identically for the REFAA, REFB,

REFBB, auxiliary REF0, auxiliary REF1, auxiliary REF2, and

auxiliary REF3 inputs by replacing all implied references to

REFA with the other reference inputs.

The user has the option of powering down unused primary

references via Register 0x2001, Bits[3:0] (see the Reference

Clock Input Resources section for a definition of primary

references).

Each reference input has a dedicated input divider (for

example, RA in Figure 60) with a programmable divide ratio

(see the Reference Dividers (R Dividers) section). Because the

reference monitor follows the R divider in the signal path, the

reference monitor essentially undersamples the reference input

clock signal for divide ratios greater than one.

Between the R divider and the reference monitor is a TDC (see

the Time to Digital Converter (TDC) section). The TDC

delivers digital (numeric) time stamps to the reference monitor,

which processes the time stamps to determine the status of the

input clock signal. Each reference TDC can connect to either

DPLL input via the digital cross point mux (see Figure 1). Even

when a reference does not connect to one of the DPLLs via the

cross point mux, the corresponding reference monitor

continues to observe the reference signal and generate status

signals accordingly.

The reference monitor uses certain user-programmable

parameters (see the Reference Monitor Controls section) to

perform various monitoring functions. The reference monitor

provides status indicators (see the Reference Monitor Status

Indicators section) that allow the user to assess the quality of

the reference input signal.

The AD9546 uses the status provided by the reference monitor

to control certain internal functions (automatic reference

switching, for example). The user has access to the status

signals via the register map or as a physical signal via the Mx

pins (see the Status and Control Pins section and Interrupt

Request (IRQ) section for more details).

REFA

TO DIGITAL CROSS

POINT MUX

RESET

NOTES

1. REGISTER ADDRESSES SHOWN FOR REFA ONLY

2. A RANGE OF BITS USES A COLON SEPARATOR

3. CERTAIN STATUS AND CONTROL BITS CAN BE ACCESSED VIA THE MX PINS

SLOW

FAST

LOS

tREF

TDC

REFERENCE

INPUT

COMPONENTS

TIME STAMP

PROCESSOR

AND JITTER

ESTIMATOR

REFERENCE MONITOR

SYSTEM CLOCK

UNSTABLE

PHASE STEP

DETECTED

USER CHANGES

INPUT MODE

USER CHANGES

tREF,

THRESHOLD, HYSTERESIS,

OR JITTER TOLERANCE

USER CHANGES R

DISCONTINUITY

NO SIGNAL

RESET

TIME

STAMPS

FAULT

BYPASS

INVALIDATE

VALIDATION TIMER

1kHz

START

DONE

END

RESET

TIMEOUT

PERIOD

tVALID

USER

CHANGES

tVALID

VALID

CLK

÷RA

REG 0x0403 TO 0x0400, BITS[29:0]

REG 0x2001,

BIT 0

REG 0x040B TO 0x0404, BITS[59:0]

REG 0x040E TO 0x040C, BITS[23:0]

REG 0x040F, BITS[2:0]

REG 0x0414 TO 0x0413, BITS[15:0]

REG 0x0412 TO 0x0410,

BITS[19:0]

REG 0x2002, BIT 0

REG 0x3005, BIT 4

REG 0x2004, BIT 0

REG 0x2003, BIT 0

REG 0x3005, BIT 3

REG 0x3005, BIT 0

REG 0x3005, BIT 1

REG 0x3005, BIT 5

REG 0x3005, BIT 2

EXCESSIVE

JITTER

EXCESS

JITTER

THRESHOLD

HYSTERESIS

JITTER TOLERANCE

JITTER

TOLERANCE

≠ 0

Figure 60. Reference Monitor

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