AD9546SLASHPCBZ datasheet(86/205 Pages) AD

Il numero della parte	AD9546/PCBZ

Spiegazioni elettronici	Dual DPLL Digitized Clock Synchronizer

PDF	205 Pages

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Produttore elettronici	AD [Analog Devices]

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AD9546

Data Sheet

Rev. 0 | Page 86 of 205

REFERENCE MONITOR RESET

The reference monitor associated with a specific reference

resets under certain conditions. A reset restarts the period and

jitter estimation process for the reference monitor. The

following list indicates the conditions that cause the reference

monitor to reset (also shown in Figure 60):

•

When the system clock indicates unstable status

•

When the user changes the mode of the input receiver, the

R divider value, the tREF value, the ΔtREF value, the jitter

tolerance value, or the hysteresis value

•

Optionally, when the reference experiences a significant

phase step as determined by the DPLL (assuming the user

enables phase step detection via Bit 7 of Register 0x2105

and Register 0x2205).

The last item requires that the user program a nonzero phase

step limit value. See the Phase Step Limit section for details

regarding the phase step limit feature.

AD9546/PCBZ Scheda tecnica(PDF) 86 Page - Analog Devices