 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
AD9546/PCBZ Scheda tecnica(PDF) 27 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9546/PCBZ Scheda tecnica(HTML) 27 Page - Analog Devices |
|
|
27 / 205 page  Data Sheet AD9546 Rev. 0 | Page 27 of 205 COMMON CLOCK SYNCHRONIZER (CCS) SPECIFICATIONS Table 26. Parameter Min Typ Max Unit Test Conditions/Comments ABSOLUTE LATENCY Time from asserting an input/output (IO) update (Bit 0 in Register 0x000F) to the CSS indicating ready status (asserting IO update constitutes insertion of a time value; see the synchronization time input in Figure 51) Fractional Seconds Format 1 μs PTP Format 3 μs BLACKOUT PERIOD 10 μs The time interval following assertion of an input synchronization event (see the synchronization input in Figure 51) before asserting an IO update to insert a time value (see the synchronization time input in Figure 51) GUARD PARAMETERS Maximum Magnitude Guard Range 0 953 ns Minimum value applies when maximum magnitude guard is disabled; maximum value is (220 − 1) × 2−40 sec Resolution 909 fs 2−40 sec Latency Guard Range 0 0.99998 sec Minimum value applies when latency guard is disabled; maximum value is 1 − 2−16 sec Resolution 15.3 μs 2−16 sec SLEW LIMITER Range 0 244 μs/sec Minimum value applies when slew limiter is disabled; Max value is (224 − 1) × 2−36 sec Resolution 14.6 ps/sec 2−36 sec/sec TIME OFFSET Range −7.63 +7.63 μs Minimum value is −2−17 sec; maximum value is (231 – 1) × 2−48 sec Resolution 3.55 fs 2−48 sec TIME SKEW Range −29.8 +29.8 ns Minimum value is −2−25s; maximum value is (223 – 1) × 2−48 sec Resolution 3.55 fs 2−48 sec USER TIME STAMPERS (UTS) SPECIFICATIONS Table 27. Parameter Min Typ Max Unit Test Conditions/Comments LATENCY Fractional Seconds Format 4 6 μs PTP Format 5 7 μs THROUGHPUT RATE The sample rate is shared among all UTSs that are connected to a time stamp source; data capture involves asserting an IO update and reading the UTS first in, first out (FIFO) registers as a contiguous 14-byte block; the indicated rate is the maximum continuous UTS traffic possible without overloading the UTS FIFO SCLK = 50 MHz with Address Looping 446 kSPS Dedicated, 100% serial port interface (SPI) utilization using address looping (loop length = 14 decimal in Register 0x0010), which eliminates the overhead of asserting an IO update prior to reading the UTS FIFO registers SCLK = 50 MHz 324 kSPS Dedicated, 100% SPI utilization SCLK = 25 MHz 16 kSPS 10% SPI utilization TIME OFFSET Range −29.8 +29.8 ns Signed 24-bit range scaled by 2−48 sec Resolution 3.55 fs 2−48 sec FIFO DEPTH 18 Samples Each UTS has a one-sample buffer, which can extend the apparent FIFO depth by a few samples beyond 18 samples |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
