AD9546SLASHPCBZ datasheet(34/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 34 of 205

JITTER GENERATION (RANDOM JITTER)

System clock frequency doubler enabled. DPLL configured with the high phase margin loop filter. The integration bandwidth for rms

jitter values is 12 kHz to 20 MHz. The effect on jitter values due to using different output driver modes is insignificant.

Device Configuration 1:

fOSC = 52 MHz crystal, fREF = 38.88 MHz, fOUT = 155.52 MHz, DPLL bandwidth (BWDPLL) = 50 Hz, phase buildout operation;

Channel 0: fVCO = 2488.32 MHz; Channel 1: VCO frequency (fVCO) = 3265.92 MHz, Q divider half divide enabled

Device Configuration 2:

fOSC = 52 MHz crystal, fREF = 30.72 MHz, fOUT = 245.76 MHz, BWDPLL = 50 Hz, internal zero delay operation;

Channel 0: fVCO = 2457.6 MHz; Channel 1: fVCO = 3686.4 MHz, Q divider half divide enabled

Device Configuration 3:

fOSC = 52 MHz crystal, fCOMP = 19.2 MHz temperature compensated crystal oscillator (TCXO), loop bandwidth of the auxiliary DPLL

servo loop (BWCOMP) = 50 Hz (see the Auxiliary DPLL Loop Bandwidth section for more details), fREF = 1 Hz, fOUT = 491.52 MHz,

BWDPLL = 0.05 Hz, phase buildout operation; Channel 0: fVCO = 2949.12 MHz; Channel 1: fVCO = 3932.16 MHz

Device Configuration 4:

fOSC = 52 MHz crystal, fCOMP = 19.2 MHz TCXO, BWCOMP = 50 Hz, fREF = 125 MHz, fOUT = 125 MHz, BWDPLL = 0.1 Hz, phase buildout

operation; Channel 0: fVCO = 2500 MHz; Channel 1: fVCO = 3250 MHz

Device Configuration 5:

fOSC = 52 MHz crystal, fREF = 25 MHz, fOUT = 312.5 MHz, BWDPLL = 50 Hz , phase buildout operation; Channel 0: fVCO = 2500 MHz;

Channel 1: fVCO = 3750 MHz

Device Configuration 6:

fOSC = 52 MHz crystal, fREF = 155.52 MHz, MHz, fOUT = (155.52 × 255/227) MHz, BWDPLL = 50 Hz; Channel 0: fVCO = 2620.5463 MHz;

Channel 1: fVCO = 3319.3586 MHz

Table 37.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

Channel 0—DPLL0, APLL0

Channel 1 powered down

fOUT = 155.52 MHz

223

Device Configuration 1

fOUT = 245.76 MHz

220

Device Configuration 2

fOUT = 491.52 MHz

235

Device Configuration 3

fOUT = 125.0 MHz

213

Device Configuration 4

fOUT = 312.5 MHz

217

Device Configuration 5

fOUT = 174.7030837 MHz

230

Device Configuration 6

Channel 1—DPLL1, APLL1

Channel 0 powered down

fOUT = 155.52 MHz

247

Device Configuration 1

fOUT = 245.76 MHz

280

Device Configuration 2

fOUT = 491.52 MHz

323

Device Configuration 3

fOUT = 125.0 MHz

243

Device Configuration 4

fOUT = 312.5 MHz

266

Device Configuration 5

fOUT = 174.7030837 MHz

264

Device Configuration 6

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