AD9546SLASHPCBZ datasheet(22/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 22 of 205

DPLL PHASE CHARACTERISTICS

Table 17.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

MAXIMUM OUTPUT PHASE

PERTURBATION

Assumes a jitter free reference; satisfies Telcordia

GR-1244 requirements; 0 ppm frequency difference

between references; reference switch initiated via

reference input

Phase Refinement Disabled

50 Hz DPLL loop bandwidth; normal phase margin

mode; frequency translation = 19.44 MHz to

155.52 MHz; 49.152 MHz signal generator used for

system clock source

Peak

±20

±175

Steady State

Phase Buildout Operation

±18

±160

Hitless Operation

Phase Refinement Enabled

50 Hz DPLL loop bandwidth; high phase margin mode;

phase refinement iterations = 4; frequency translation

= 19.44 MHz to 155.52 MHz; 49.152 MHz signal

generator used for system clock source

Peak

±5

±44

Steady State

Phase Buildout Operation

±4

±43

Hitless Operation

PHASE SLEW LIMITER

0.001

250

µs/sec

See the AN-1420 Application Note, Phase Buildout and

Hitless Switchover with Digital Phase-Locked Loops

(DPLLs)

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