AD9546SLASHPCBZ datasheet(89/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 89 of 205

DEMODULATOR SENSITIVITY

Modulated input signals exhibiting a small change in pulse width

require more sensitivity than those that exhibit a large change.

To control the demodulator sensitivity to pulse width changes,

use Bits[1:0] in Register M per the register legend in Figure 62.

The demodulator defaults to its most sensitive setting, 00 (binary).

Increasing the binary value decreases the sensitivity, with 11

(binary) constituting the least sensitive setting. Decreased

sensitivity implies the need for more robust modulation events

(that is, larger Δt in Figure 63) for reliable demodulation.

DEMODULATOR PERSISTENCE

When the demodulator detects a modulation event, it generates

a single demodulator clock pulse (see Figure 62) lasting one

tCARRIER period. Because demodulation events normally occur at

intervals of tGRID, the demodulator clock signal consists of single

pulses occurring at the tGRID rate. The demodulator clock pulse

synchronizes the R divider and causes the reference TDC to tag

the accompanying time stamp. Thus, tagged reference time stamps

occur at the tGRID rate (see the Demodulator Synchronization

section).

Note that if the incoming modulation events stop occurring,

the demodulator clock pulses cease and the TDC stops

generating tags. Assuming the TDC tags route to one of the

DPLLs, the absence of tags causes the DPLL to unlock. The

persistence feature provides a mechanism for the demodulator

to continue to generate demodulator clock pulses at the tGRID

rate when modulation events are no longer present at the input,

thereby preventing the DPLL from losing lock.

The user controls the persistence functionality via Bit 6 in

demodulator clock signal only occurs when the demodulator

detects a modulation event. When D6 = 1 (default), the

demodulator learns the modulation period (which is tGRID) and

continues to generate demodulator clock pulses at the tGRID rate.

Figure 64 shows the timing of the demodulator clock signal.

The demodulator clock signal is available via an appropriately

configured Mx status pin (see the Status and Control Pins section).

Note that if the demodulator loses synchronization (for

example, when incoming modulation events go off grid), the

demodulator requires at least three consecutive tGRID intervals

(with valid modulation events) to resynchronize the persistence

mechanism. Because the demodulator requires three consecutive

tGRID intervals (with persistence enabled) for resynchronization,

the occurrence of an occasional off grid modulation event does

not cause the persistence mechanism to realign the demodulator

output clock and resynchronize the R divider. Instead, the

persistence mechanism effectively filters out the occasional

occurrence of off grid modulation events.

DEMODULATOR BANDWIDTH

The demodulators operate within two overlapping frequency

bands: Band 0 and Band 1. The user must select the appropriate

demodulator bandwidth (based on the input carrier frequency)

via Bit 0 in Register N per the register legend in Figure 62.

Logic 0 selects Band 0, and Logic 1 (default) selects Band 1.

Note that demodulator bandwidth control applies to a group of

four demodulators rather than an individual demodulator.

Thus, the user must ensure that all demodulators of the same

group that are actively demodulating have carrier frequencies

within the specified frequency range.

TIME

MODULATION

EVENT

BASE

EDGE

SYNC EDGE

tGRID

MODULATED

CARRIER

DEMOD

CLK TIMING

FOR THIS EXAMPLE:

tGRID = 10 × tCARRIER

tCARRIER

MODULATION EVENTS OCCUR

AT INTERVALS OF

tGRID

MODULATION

EVENT

BASE

EDGE

SYNC EDGE

tGRID

Figure 64. Demodulator Synchronization

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