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AD9546/PCBZ Scheda tecnica(PDF) 26 Page - Analog Devices

Il numero della parte AD9546/PCBZ
Spiegazioni elettronici  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ Scheda tecnica(HTML) 26 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 26 of 205
TIME TO DIGITAL CONVERTER (TDC) SPECIFICATIONS
Table 23.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TDCs
Frequency Range
200
kHz
Pulse Width
5
ns
Time Stamp Jitter
Root Mean Square (TDCJrms)
5
11
ps
Peak (TDCJpk)
250
ps
Retrigger Blackout Period
4.9
µs
Interval between successive rising edges at the TDC input
Start-Up Time
6
ms
The time required, after the system clock PLL locks, before
the TDCs can generate time stamps
AUXILIARY NCO SPECIFICATIONS
Table 24.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
NCOs
Auxiliary NCO 0 and auxiliary NCO 1
Fundamental Frequency
Range
1
65,535
Hz
Quantization
1.27
1.37
pHz
pHz is picohertz
Phase Slew Limiter
5
232
ppb
Actual units are fractional part (ideal)/actual unit interval (UI)
Output Signal
Pulse Width
38
ns
Duty Cycle
45
55
%
Assumes the device is programmed to produce a nominal
pulse width of 50%
Quantization
1.4
ns
COMMON CLOCK DPLL SPECIFICATIONS
Table 25.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range
0
65,535
ps
Programmed values < 10 ps not recommended
Threshold Resolution
1
ps
Post Detection Delay Range
0
65,535
ms
REFERENCE MONITOR
Loss of Reference Detection Time
2 × tPFD
µs
tPFD = R/fREF, where R is the reference input divider
value and fREF is the reference input frequency in MHz
Input Period Deviation Limit
3.125
%
Relative to the programmed value of the reference
period, tREF
Reference Validation Delay
2
ms
Applies only to the common clock DPLL secondary
frequency source (see the Common Clock Reference
Switchover section)



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