AD9546SLASHPCBZ datasheet(95/205 Pages) AD

95 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 95 of 205

Q DIVIDER CLOCK SOURCE SELECTION

Each pair of Q dividers shares a common clock input (see

Figure 67) that originate from one of two sources.

•

From the output of the associated APLL channel of the

Q divider.

•

From the output of the system clock PLL VCO

(~2.3 GHz).

The first source is the normal (default) operating mode, which

provides frequency translation from a reference input to the

distribution output via the corresponding PLL channel. The

second source is the output frequency of the system clock PLL,

which is useful for clocking certain peripheral devices (a

microprocessor, for example). In this scenario, the user can

employ an optional external electronically erasable programmable

read only memory (EEPROM) to download a device

configuration that provides an output clock signal at power up

via the system clock source path (see the EEPROM Usage

section).

Table 62 shows the register address and bits associated with

selecting the clock source for the Q dividers. Logic 0 (default)

selects the output of the corresponding APLL as the Q divider

clock source, whereas Logic 1 selects the output of the system

clock PLL as the Q divider clock source.

Table 62. Q Divider Clock Source Selection

Q Divider

Bit

Q0A and Q0AA

0x10DA

Q0B and Q0BB

0x10DA

Q0C and Q0CC

0x10DA

Q1A and Q1AA

0x14DA

Q1B and Q1BB

0x14DA

When the AD9546 is configured with the system clock as the

clock source for a Q divider pair, use Bit 0 (system clock

synchronization mask) of Register 0x10DA and Register 0x14DA

to prevent those particular dividers from being resynchronized

every time a synchronization trigger occurs (see the Distribution

Output Clock Synchronization section). When this bit is set,

any Q divider associated with a specific PLL channel and with

the system clock as the clock source is immune to synchronization

events. This feature is particularly useful for outputs that serve

as the clock source to a microprocessor, for example, because

an unmasked synchronization event disrupts the clock signal of

the processor.

In some applications, when more than one Q divider pair uses

the system clock as its clock source, it may be desirable to

synchronize at least two of those Q divider pairs using the

system clock synchronization mask bit of Register 0x10DA and

(see the Distribution Output Clock Synchronization section),

then program the corresponding mask system clock

synchronization bit to Logic 1. To reconfigure the affected Q

dividers by changing the divide ratio, for example, the user

must first program the corresponding system clock

synchronization mask bit to Logic 0.

INTEGER DIVISION

The Q divider divide ratio (Q) depends on a 32-bit unsigned

integer in the register ranges shown in Table 63. To program

the divide ratio, write the value of Q into the corresponding

address range and then set the IO update bit.

The range of Q is 1 to 4,294,967,295.

For example, to establish a divide ratio of Q = 1,000,000, the

required 32-bit value is 1,000,000 (0x 000F 4240 hexadecimal).

Table 63. Q Divider Divide Ratio Address Ranges

Q Divider

Q0A

0x1100 to 0x1103

Q0AA

0x1109 to 0x110C

Q0B

0x1112 to 0x1115

Q0BB

0x111B to 0x111E

Q0C

0x1124 to 0x1127

Q0CC

0x112D to 0x1130

Q1A

0x1500 to 0x1503

Q1AA

0x1509 to 0x150C

Q1B

0x1512 to 0x1515

Q1BB

0x151B to 0x151E

A value of 0 (default) sets a divide ratio of 1, which is an

unsupported divide ratio. Therefore, at power-up or after

resetting the device, the user must program the Qxy divider

ratio bit fields with values greater than 1 to enable the

corresponding Q dividers.

Although it is possible to program a different divide ratio for

each Q divider of a Q divider pair, the recommendation is to

avoid doing so because a Q divider pair with differing divide

ratios results in two different output frequencies and can cause

cross coupling issues (due to the close physical proximity of the

corresponding output drivers). The intent is for Q divider pairs

to operate with the same output frequency but with the option

to control the relative phase between the outputs (see the

Distribution Phase Offset Control section).

AD9546/PCBZ Scheda tecnica(PDF) 95 Page - Analog Devices

AD9546/PCBZ Scheda tecnica(HTML) 95 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL