AD9546SLASHPCBZ datasheet(33/205 Pages) AD

33 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 33 of 205

I2C Mode

Table 36.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (AS INPUTS)

Valid for VDDIOA = 1.8 V, 2.5 V, and 3.3 V

Input Voltage

Logic 1

% of VDDIOA

Logic 0

0.3 × VDDIOA

Input Current

−10

+10

µA

For VIN = 10% to 90% of VDDIOA

Hysteresis of Schmitt Trigger

Inputs

1.5

% of VDDIOA

SDA (AS OUTPUT)

Output Logic 0 Voltage

0.2

Output current (IOUT) = 3 mA

Output Fall Time from VIH

Minimum to VIL Maximum

20 + 0.1 × CB

250

10 pF ≤ CB ≤ 400 pF; CB is the bus

capacitance

TIMING

SCL Clock Rate

400

kHz

Bus Free Time Between a Stop and

Start Condition, tBUF

1.3

µs

Repeated Start Condition Setup

Time, tSU; STA

0.6

µs

Repeated Hold Time Start

Condition, tHD; STA

0.6

µs

After this period, the first clock pulse is

generated

Stop Condition Setup Time, tSU; STO

0.6

µs

Low Period of the SCL Clock, tLOW

1.3

µs

High Period of the SCL Clock, tHIGH

0.6

µs

SCL/SDA Rise Time, tR

20 + 0.1 × CB

300

SCL/SDA Fall Time, tF

20 + 0.1 × CB

300

Data Setup Time, tSU; DAT

100

Data Hold Time, tHD; DAT

100

Capacitive Load, CB

400

Applies to individual bus lines

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