AD9546SLASHPCBZ datasheet(96/205 Pages) AD

96 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 96 of 205

HALF INTEGER DIVISION

The Q dividers are unique in that they support half integer

division, a benefit of the Q dividers counting both the rising

and falling edges of the input clock. To enable half integer

division for the corresponding Q divider, use Bit 5 (half integer

divide) of the appropriate register per Table 64.

Table 64. Q Divider Half Integer Divide Register Address

Q Divider

Q0A

0x1108

Q0AA

0x1111

Q0B

0x111A

Q0BB

0x1123

Q0C

0x112C

Q0CC

0x1135

Q1A

0x1508

Q1AA

0x1511

Q1B

0x151A

Q1BB

0x1523

When the half integer divide bit is Logic 1, it effectively adds an

extra 0.5 to the divide ratio prescribed by the corresponding

32-bit Q divider ratio. The value of the half integer divide bit

does not become effective until the user sets the IO update bit.

For example, assume the Q divider ratio is 100. If the associated

enable half integer divide bit is Logic 1, the total divide ratio is

100.5.

Q DIVIDER RESET

Each Q divider has a dedicated Q divider reset bit via Bits[1:0]

of the registers shown in Table 65, where Bit 0 applies to the

first Q divider in the row (for example, Q0A) and Bit 1 applies

to the second Q divider in the row (for example, Q0AA).

The Q divider reset bits allow the user to reset the Q dividers

manually in applications that do not require output clock

synchronization. In most cases, however, there is no need to set

these bits during normal operation because the synchronization

controller automatically handles the Q divider reset function

(see the Distribution Output Clock Synchronization section).

Table 65. Output Driver Reset Register Address

Q Divider

Q0A and Q0AA

0x2102

Q0B and Q0BB

0x2103

Q0C and Q0CC

0x2104

Q1A and Q1AA

0x2202

Q1B and Q1BB

0x2203

Q DIVIDER CONSTRAINTS

Changing the divide ratio of any one of the Q dividers invokes a

synchronization process (see the Autoreconfiguration

Synchronization Trigger section). The act of changing the

divide ratio of a single Q divider causes a disturbance of all the

output clock signals of the associated PLL channel. Therefore, it

is not possible to change the divide ratio of one Q divider

without disturbing all the output clock signals of the associated

PLL channel.

When the system clock is the selected clock source for a

Q divider pair (see the Distribution Output Clock Synchronization

section), an unlock event on the system clock may cause the

Q divider pair to enter an invalid state. Recovery from this state

requires a divider reset. Therefore, after a system clock unlock

event, the user must follow these steps:

1. Calibrate the system clock (see the System Clock

Calibration section).

2. Calibrate APLL0 and APLL1 (see the VCO Calibration

section).

3. Reset any Q dividers (see the Q Divider Reset section)

using the system clock as an input clock source.

4. Synchronize output distribution (see the Distribution

Output Clock Synchronization section).

When using embedded output clock modulation to modulate

the Q divider output (see the Distribution Embedded Output

Clock Modulation section), a minimum Q divider divide ratio

is necessary.

Qxy ≥ 8

where:

x = 0 or 1.

y = A, B, or C.

When employing the N shot triggering mechanism to trigger a

Q divider (see the N Shot Triggering section), a minimum

Q divider divide ratio of 8 is necessary.

Qxy ≥ 8

where:

x = 0 or 1.

y = A, B, or C.

HITLESS/ZERO DELAY FEEDBACK

When configured for hitless or zero delay operation, the DPLL

of the affected PLL channel requires a feedback clock signal to

its N divider from one of the distribution outputs. This

feedback mechanism is via the hitless or zero delay feedback

and synchronization block of the N shot/PRBS controller in

Figure 68. Selection of the desired feedback path is via the

frequency translation profiles. See the Internal Zero Delay

(Hitless) Mode section in the Frequency Translation Loops

section for programming details.

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