AD9546SLASHPCBZ datasheet(32/205 Pages) AD

Il numero della parte	AD9546/PCBZ

Spiegazioni elettronici	Dual DPLL Digitized Clock Synchronizer

PDF	205 Pages

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Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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32 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 32 of 205

SERIAL PORT SPECIFICATIONS

SPI Mode

Table 35.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CSB

Valid for VDDIOA = 1.8 V, 2.5 V, and 3.3 V

Input Voltage

Logic 1

VDDIOA − 0.4

Logic 0

0.4

Input Current

Logic 1

µA

Logic 0

µA

SCLK

Input Voltage

Logic 1

VDDIOA − 0.4

Logic 0

0.4

Input Current

Logic 1

µA

Logic 0

µA

SDIO

As an Input

Input Voltage

Logic 1

VDDIOA − 0.4

Logic 0

0.4

Input Current

Logic 1

µA

Logic 0

µA

As an Output

Output Voltage

1 mA load current

Logic 1

VDDIOA − 0.2

Logic 0

0.2

SDO

Output Voltage

1 mA load current

Logic 1

VDDIOA − 0.2

Logic 0

0.2

Leakage Current

±1

µA

SDO inactive (high impedance)

TIMING

Valid for VDDIOA = 1.8 V, 2.5 V, and 3.3 V

SCLK

Clock Rate, 1/tCLK

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

2.2

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CSB to SCLK Setup, tS

1.5

CSB to SCLK Hold, tC

CSB Minimum Pulse Width High

tCLK

AD9546/PCBZ Scheda tecnica(PDF) 32 Page - Analog Devices

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