AD9546SLASHPCBZ datasheet(75/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 75 of 205

Direct Path

Select the direct path by programming Register 0x0201, Bit 3, to

Logic 0. Refer to Figure 31 for connecting a TCXO or OCXO

with a 3.3 V output to the XOA and XOB pins.

The direct path supports low frequency LVPECL, LVDS, CMOS,

or sinusoidal clock sources as a reference to the system clock PLL.

For a sinusoidal source, however, it is best to use a frequency of

50 MHz or greater. The low slew rate of lower frequency sinusoids

tends to yield nonoptimal noise performance.

The direct path has a differential receiver with a self bias of

0.75 V dc. Generally, the presence of the bias voltage

necessitates the use of ac coupling between the external source

and the XOA and XOB pins. Furthermore, when using a 3.3 V

CMOS oscillator as the system clock PLL reference source, in

addition to ac coupling, it is important to use a voltage divider

to reduce the 3.3 V swing to a maximum of 1.14 V (note that

the optimal voltage swing is 800 mV p-p).

Degraded phase noise performance typically occurs when the

frequency at the input of the PFD of the system clock PLL is

less than 50 MHz. For optimal phase noise performance, use

the quartz crystal resonator path with a crystal resonator

frequency ≥ 50 MHz, the frequency doubler enabled, and the

device configured to use system clock Compensation Method 3

(see the System Clock Compensation section).

PRESCALE DIVIDER

The system clock PLL includes an input prescale divider

programmable for divide ratios of 1 (default), 2, 4, or 8. The

purpose of the divider provides flexible frequency planning for

mitigating potential spurs in the output clock signals of the

AD9546. The user selects the divide ratio via Register 0x0201,

Bits[2:1]. The corresponding divide value is 2J, where J is the

decimal value of the 2-bit number comprising Register 0x0201,

Bits[2:1].

For example, a value of 10 (binary) in Register 0x0201 Bits[2:1],

means J = 2 (decimal), making the divide ratio = 4 (2J = 22 = 4).

FEEDBACK DIVIDER

The output of the system clock PLL constitutes the system clock

frequency, fS. The system clock frequency depends on the value of

the feedback divider (K in Figure 57). The feedback divide ratio has

a range of 4 to 255, which the user programs via Register 0x0200,

Bits[7:0]. The programmed register value is the divide ratio. For

example, a programmed value of 100 (0x64 hexadecimal) yields a

divide ratio of 100.

SYSTEM CLOCK PLL OUTPUT FREQUENCY

Calculate the system clock frequency, fS, as follows:

OSC

where:

fOSC is the input frequency.

K is the feedback divide ratio.

J is the input divide ratio. J = ½ when using the 2× frequency

multiplier.

The user must choose fOSC, K, and J such that fS satisfies the

VCO range of 2250 MHz to 2415 MHz.

SYSTEM CLOCK PLL LOCK DETECTOR

The system clock PLL features a simple lock detector that com-

pares the time difference between the reference and feedback

clock edges. The user can check the status of the lock detector

via Register 0x3001, Bit 0, where Logic 1 indicates locked and

Logic 0 indicates unlocked.

SYSTEM CLOCK STABILITY TIMER

Because time processing blocks within the AD9546 depend on

the system clock generating a stable frequency, the system clock

PLL provides an indication of the status. The status of the

system clock PLL is available to the user as well as directly to

certain internal time keeping blocks.

At initial power-up, the system clock status is unknown and

reported as being unstable. However, after the user programs

the system clock registers and the system clock PLL VCO

calibrates, the system clock PLL locks shortly thereafter.

Even though the system clock PLL may indicate a lock status,

the user can introduce an additional holdoff period, in units of

milliseconds (10−3 sec), via an unsigned 20-bit integer in

Bits[19:0] of Register 0x0209 to Register 0x0207

(Register 0x0209, Bit 3 denotes the MSB). There are two special

values: 0 and 1,048,575. A value of 0 causes the system clock to

indicate an unstable status regardless of the actual state of the

system clock (useful for debugging purposes, because the user

can force an unstable status indication even though the PLL is

stable). A value of 1,048,575 is invalid because it makes Register

0x3001, Bit 1 undefined when the system clock PLL is

unlocked.

SYSTEM CLOCK CALIBRATION

The VCO in the system clock PLL requires a calibration

sequence. At power-up, part of the initialization sequence of

the device includes system clock calibration. In general, the

user is not required to calibrate the system clock manually.

However, changing any of the system clock parameters that

result in a new VCO frequency requires a manual system clock

calibration via Register 0x2000, Bit 2, is not an autoclearing bit.

Therefore, the full programming sequence is to write Logic 1,

assert an IO update, write Logic 0, and assert an IO update.

Furthermore, whenever the system clock PLL is in the process

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