AD9546SLASHPCBZ datasheet(40/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 40 of 205

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

OUT0AN

Output

HCSL, LVDS,

CML

PLL0 Complementary Output 0A.

OUT0BP

Output

HCSL, LVDS,

CML

PLL0 Output 0B.

OUT0BN

Output

HCSL, LVDS,

CML

PLL0 Complementary Output 0B.

16, 21, 44

DNC

No connect

Do Not Connect. Leave the DNC pins floating.

OUT0CP

Output

HCSL, LVDS,

CML

PLL0 Output 0C.

OUT0CN

Output

HCSL, LVDS,

CML

PLL0 Complementary Output 0C.

OUT1BP

Output

HCSL, LVDS,

CML

PLL1 Output 1B.

OUT1BN

Output

HCSL, LVDS,

CML

PLL1 Complementary Output 1B.

OUT1AP

Output

HCSL, LVDS,

CML

PLL1 Output 1A.

OUT1AN

Input/

Output

HCSL, LVDS,

CML

PLL1 Complementary Output 1A.

LF1

Input/

output

Loop filter

for APLL1

Loop Filter Node for APLL1. Connect a 3.9 nF capacitor from the LF1 pin to Pin 30

(LDO1).

LDO1

Input

LDO bypass

APLL1 Loop Filter Voltage Regulator. Connect a 0.22 μF capacitor from the

LDO1 pin to ground. LDO1 is the ac ground reference for the integrated APLL1

loop filter.

32, 33, 35, 36, 37

M0, M1,

M2, M3, M4

Input/

output

CMOS

Configurable Input/Output Pins. Mx are status and control pins. Changes to the

VDDIOB supply voltage affect the VIH and VOH values for these Mx pins. M3 and

M4 have internal 100 kΩ pull-down resistors. M0, M1, and M2 do not have

internal resistors.

VDDIOB

Input

Power

Mx Pin Power Supply. The VDDIOB power supply powers the digital section

that controls the M0 to M4 pins. Valid supply voltages are 1.8 V, 2.5 V, or 3.3 V.

The VDDIOB pin can be connected to the VDD supply bus if 1.8 V operation is

desired.

REFB

Input

1.8 V single-

ended or

differential

input

Reference B Input. This internally biased REFB input is typically ac-coupled.

When configured in this manner, REFB can accept any differential signal with a

single-ended swing up to the VDD power supply. If dc-coupled, the REFB input

can be LVDS or single-ended 1.8 V CMOS.

REFBB

Input

1.8 V single-

ended or

differential

input

Reference BB Input or Complementary Reference B Input. If REFB is in

differential mode, the REFB complementary signal is on the REFBB pin. No

connection is necessary to the REFBB pin if REFB is a single-ended input and

REFBB is not used.

XOA

Input

Differential

input

System Clock Input. XOA contains internal dc biasing and must be ac-coupled with

a 0.1 μF capacitor except when using a crystal. When a crystal is used, connect

the crystal across XOA and XOB. A single-ended CMOS input is also an option,

but it can produce spurious spectral content when the duty cycle is not 50%.

When using XOA as a single-ended input, connect a 0.1 μF capacitor from XOB

to ground.

XOB

Input

Differential

input

Complementary System Clock Input. XOB is the complementary signal to XOA.

XOB contains internal dc biasing and must be ac-coupled with a 0.1 μF capacitor

except when using a crystal. When a crystal is used, connect the crystal across

XOA and XOB.

REFAA

Input

1.8 V single-

ended or

differential

input

Reference AA input or Complementary REFA Input. If REFA is in differential

mode, the REFA complementary signal is on the REFAA pin. No connection is

necessary to the REFAA pin if REFA is a single-ended input and REFAA is not

used. If dc-coupled, the REFAA input is single-ended 1.8 V CMOS.

REFA

Input

1.8 V single-

ended or

differential

input

Reference A Input. The internally biased REFA input is typically ac-coupled.

When REFA is configured in this manner, REFA can accept any differential

signal with a single-ended swing up to the VDD power supply. If dc-coupled,

the input can be LVDS or single-ended 1.8 V CMOS.

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