AD9546SLASHPCBZ datasheet(14/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 14 of 205

REFx TO REFx INPUT TIMING SKEW

The values shown in Table 8 indicate the internal timing skew between a clock signal applied to the REFA input (base input) and the

same clock signal applied to the REFAA, REFB, or REFBB input (target input) with both clock signals time aligned at the device pins.

The top section of the table indicates timing skew for REFA configured as the CMOS 1.2 V base input against REFx (x = AA, B, BB) as

the target input with various target input configurations. The bottom section of the table captures timing skew for REFA as the base

input with input configurations other than CMOS 1.2 V against REFB CMOS 1.2 V as the target input, which establishes REFB CMOS

1.2 V as a common target for different REFA input configurations. The common target allows the user to extrapolate the skew to other

target inputs when REFA is configured for other than CMOS 1.2 V.

Table 8.

Parameter

Min

Typ

Max

Unit

TIMING SKEW—REFA CMOS 1.2 V BASE REFERENCE INPUT

Target Reference Input

REFAA CMOS 1.2 V

−190

−70

+45

REFAA CMOS 1.8 V

−95

+130

+330

REFAA AC-Coupled Single-Ended

−70

+55

+215

REFB CMOS 1.2 V

−155

−15

+125

REFBB CMOS 1.2 V

−170

−30

+110

REFB Differential, LVDS

−250

−100

+50

REFB Differential, DC-Coupled

−190

+30

+270

TIMING SKEW—OTHER BASE REFERENCE INPUT CONFIGURATIONS

REFA CMOS 1.8 V Base Reference Input

Target Reference Input

REFB CMOS 1.2 V

−180

−5

+155

REFA AC-Coupled, Single-Ended Base Reference Input

Target Reference Input

REFB CMOS 1.2 V

−200

−55

+95

REFA Differential, LVDS Base Reference Input

Target Reference Input

REFB CMOS 1.2 V

195

340

REFA Differential, DC-Coupled Base Reference Input

Target Reference Input

REFB CMOS 1.2 V

−145

+85

+285

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