 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
AD9546/PCBZ Scheda tecnica(PDF) 56 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9546/PCBZ Scheda tecnica(HTML) 56 Page - Analog Devices |
|
|
56 / 205 page  AD9546 Data Sheet Rev. 0 | Page 56 of 205 COMMON CLOCK DPLL (CCDPLL) OVERVIEW The CCDPLL embodies most of the hardware associated with the auxiliary DPLL (see the Compensation Method 3 subsection of the System Clock Compensation section). However, the CCDPLL incorporates additional enhancements to the auxiliary DPLL hardware to meet the needs of a digitized clocking system. Figure 50 shows a functional block diagram of the CCDPLL. COMMON CLOCK REFERENCES The CCDPLL supports two independent time stamp sources as common clock reference (CCR) frequency inputs. CCR0 is the primary frequency reference, whereas CCR1 is the secondary frequency reference. The primary and secondary distinction matters with respect to the handling of the CCDPLL of automatic switching between references (see the Common Clock Reference Switchover section). When employing only a single CCR, the user must use CCR0. That is, assigning a reference to CCR1 with no reference assigned to CCR0 is an invalid condition. It is best practice to use REFB, REFBB, or both input pins for the common clock DPLL reference frequency because the REFB and REFBB inputs are the only reference inputs that provide access to the analog loopback function (see the Analog Clock Loopback section). CCR Enable and CCR Frequency Source Each CCR has an enable bit (Bit 7 of Register 0x0D10 and/or Register 0x0D20 for CCR0 and CCR1, respectively). Logic 0 (default) disables the CCR, whereas Logic 1 enables it. When operating the device with both CCRs, the enable bit gives the user a simple mechanism to force a reference switchover (see the Common Clock Reference Switchover section) by disabling the active CCR. The user can independently assign each CCR to a specific time stamp source (via Bits[4:0] of Register 0x0D10 and Register 0x0D20 for CCR0 and CCR1, respectively). The default value, 0x31, is the null selection. That is, the associated CCR has no time stamp source. For CCR0, programming a nondefault value for the enable or time stamp source selection settings results in the CCR0 time stamp source selection overriding the reference TDC selection of the auxiliary DPLL (see the Compensation Method 3 subsection of the System Clock Compensation section). CCDPLL REF MON LOCAL TIME SCALE GENERATOR LOCAL TIME SCALE CORE CLOCK (~25MHz BITS) COMMON CLOCK LOOP CONTROLLER LOOP FILTER TARGET REFERENCE PERIOD PROCESSOR UPDATES ON ARRIVAL OF TIME STAMPS FROM ACTIVE CCR CCR0 TIME STAMPS TIME STAMP PROCESSOR CCDPLL REF MON REG 0x0D15 TO 0x0D12, BITS[31:0] REG 0x0D1A TO 0x0D16, BITS[39:0] NUM0 DEN0 REG 0x0D25 TO 0x0D22, BITS[31:0] REG 0x0D2A TO 0x0D26, BITS[39:0] REG 0x0D10, BIT 7 ENBL0 REG 0x0D20, BIT 7 REG 0x0D10, BITS[4:0] REG 0x0D20, BITS[4:0] ENBL1 CCR0 SOURCE CCR1 SOURCE TIME STAMPS NUM DEN 0 1 ACTIVE SOURCE R REF TARGET REFERENCE PERIOD PERIOD ERROR LOCK DETECT HOLDOVER REGISTER REG 0x040B TO 0x0404, BITS[59:0] REG 0x042B TO 0x0424, BITS[59:0] REG 0x048B TO 0x0484, BITS[59:0] REG 0x044B TO 0x0444 ,BITS[59:0] REG 0x046B TO 0x0464, BITS[59:0] REG 0x04EB TO 0x04E4, BITS[59:0] REG 0x04AB TO 0x04A4, BITS[59:0] REG 0x04CB TO 0x04C4, BITS[59:0] REG 0x0403 TO 0x0400, BITS[29:0] REG 0x0423 TO 0x0420, BITS[29:0] REG 0x0443 TO 0x0440, BITS[29:0] REG 0x0463 TO 0x0460, BITS[29:0] REG 0x0483 TO 0x0480, BITS[29:0] REG 0x04A3 TO 0x04A0, BITS[29:0] REG 0x04C3 TO 0x04C0, BITS[29:0] REG 0x04E3 TO 0x04E0, BITS[29:0] REG 0x0286 TO 0x0285, BITS[15:0] BANDWIDTH REG 0x0D01 TO 0x0D00, BITS[15:0] THRESHOLD REG 0x0D02, BITS[7:0] FILL REG 0x0D03, BITS[7:0] DRAIN REG 0x0D05 TO 0x0D04, BITS[15:0] STABILITY HOLDOVER LOCKED REG 0x3002, BIT 1 REG 0x0D40, BIT 4 REG 0x0D40, BIT 5 CCR0 VALID CCR1 VALID FROM TIME STAMP SOURCES NOTES 1. A RANGE OF BITS USES A COLON SEPARATOR REG 0x0206 TO 0x0202, BITS[39:0] SYSCLK REF FREQ CCR0 INDEX CCR1 INDEX CCR1 INDEX CCR0 INDEX 0 ACTIVE SOURCE 1 CCR1 TIME STAMPS REG 0x0D40, BIT 3 REG 0x0D40, BIT 0 ACTIVE SYSTEM CLOCK COMPENSATION SUBSYSTEM INTERFACE COMPX FROM TIME STAMP SOURCES NUM1 DEN1 REG 0x0D40, BIT 1 CF3 Figure 50. Common Clock DPLL Block Diagram |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
