AD9546SLASHPCBZ datasheet(10/205 Pages) AD

10 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 10 of 205

REFERENCE INPUTS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE

Differential mode specifications assume ac coupling of the

input signal to the reference input pins

Frequency Range

Sinusoidal Input

750

MHz

Lower limit dependent on input slew rate

Low Voltage Positive Emitter

Coupled Logic (LVPECL)

Input

750 × 106

Lower limit dependent on ac coupling

LVDS Input

500 × 106

Assumes an LVDS minimum of 494 mV p-p differential

amplitude; lower limit dependent on ac coupling

Slew Rate

>4.1

V/µs

Required for proper reference monitor operation; output

jitter degradation can occur for slew rates < 35 V/µs

Common-Mode Input Voltage

0.64

Internally generated self bias voltage

Differential Input Amplitude

Peak-to-peak differential voltage swing across pins required

to ensure switching between logic levels as measured with a

differential probe; instantaneous voltage on either pin must

not exceed 1.3 V

fIN < 500 MHz

350

2100

mV p-p

fIN = 500 MHz to 750 MHz

500

2100

mV p-p

Differential Input Voltage

Hysteresis

100

Input Resistance

kΩ

Equivalent differential input resistance

Input Pulse Width

LVPECL

600

LVDS

900

DC-COUPLED, LVDS-COMPATIBLE

MODE

Applies for dc coupling to an LVDS source

Frequency Range

450 × 106

Slew Rate

>1.2

V/µs

Required for proper reference monitor operation; output

jitter degradation can occur for slew rates < 35 V/µs

Common-Mode Input Voltage

1.125

1.375

Differential Input Amplitude

400

1200

mV p-p

Differential voltage across pins required to ensure switching

between logic levels; instantaneous voltage on either pin

must not exceed the supply rails

Differential Input Voltage

Hysteresis

100

Input Resistance

kΩ

Input Pulse Width

SINGLE-ENDED MODE

Single-ended mode specifications assume dc coupling of the

input signal to the reference input pins

1.2 V CMOS

Frequency Range

500 × 106

Assumes dc-coupled input signal to the reference input pins

Input Voltage

High, VIH

0.78

1.38

Low, VIL

0.42

Input Resistance

kΩ

Slew Rate

V/µs

Required for proper reference monitor operation; output

jitter degradation can occur for slew rates < 35 V/µs

Input Pulse Width

900

1.8 V CMOS

Frequency Range

500 × 106

Assumes dc-coupled input signal to the reference input pins

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