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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AD9546/PCBZ Scheda tecnica(PDF) 23 Page - Analog Devices |
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AD9546/PCBZ Scheda tecnica(HTML) 23 Page - Analog Devices |
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23 / 205 page  Data Sheet AD9546 Rev. 0 | Page 23 of 205 DPLL PROPAGATION DELAY DPLL propagation delay is the difference in clock edge timing at the output (OUTxyP/OUTxyN) relative to the REFA input (1.2 V CMOS mode). To accommodate edge timing measurements, the DPLL is configured for internal zero delay (hitless) operation and with a 1:1 frequency translation ratio: fREF = fOUT = 10 MHz. Delay compensation is not active (see the Delay Compensation section). Absolute delay values use Q Divider QxA as feedback for DPLLx, where x is 0 or 1. The data shows propagation delay for various output driver configurations (single-ended, differential), driver modes (HCSL, CML), and driver output current. The data also shows the propagation delay to outputs associated with a Q divider that is not the Q divider used for DPLL feedback. Also captured is the delay when using DPLL1 instead of DPLL0. Relative delay values show the impact of using other Q dividers for DPLL feedback (relative to QxA for DPLLx, where x is 0 or 1). For the propagation delay variation due to using a reference input mode other than 1.2 V CMOS, use Table 8. Table 18. Parameter Min Typ Max Unit Test Conditions/Comments ABSOLUTE DELAY REFA to OUT0AP Q0A = DPLL0 feedback; driver output = single-ended CML at 12.5 mA 1055 1265 1430 ps CML at 15 mA 1065 1270 1430 ps HCSL at 12.5 mA 1180 1385 1550 ps HCSL at 15 mA 1145 1345 1515 ps REFA to OUT0AN 1185 1390 1565 ps Driver output = single-ended HCSL at 15 mA REFA to OUT0A1 Driver output = differential CML at 7.5 mA 805 1000 1180 ps CML at 15 mA 760 955 1130 ps HCSL at 7.5 mA 845 1030 1200 ps HCSL at 15 mA 785 975 1155 ps REFA to OUT0B1 770 960 1140 ps Driver output = differential HCSL at 15 mA REFA to OUT0C1 785 970 1145 ps Driver output = differential HCSL at 15 mA REFA to OUT1AP 1150 1370 1565 ps Q1A = DPLL1 feedback; driver output = single-ended HCSL at 15 mA REFA to OUT1A1 810 985 1140 ps Driver output = differential HCSL at 15 mA REFA to OUT1B1 740 970 1180 ps Driver output = differential HCSL at 15 mA RELATIVE DELAY2 With respect to Q0A (PLL0) or Q1A (PLL1) QxAA 14 ps QxB 9 ps QxBB 23 ps Q0C 36 ps Q0CC 50 ps 1 OUTxy refers to Output xy where x is 0 or 1, and y is A, B, or C. See the Distribution Clock Output Drivers Overview section for more information about the output drivers. 2 Qxy denotes a specific Q divider in the clock distribution section, where x is 0 or 1, and y is AA, B, BB, C, or CC. |
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