WM8281ECSSLASHR datasheet(196/392 Pages) CIRRUS

196 / 392 page

WM8281

196

Rev 4.0

OUTPUT SIGNAL PATH NOISE GATE CONTROL

The WM8281 provides a digital noise gate function for each of the output signal paths. The noise gate

ensures best noise performance when the signal path is idle. When the noise gate is enabled, and the

applicable signal level is below the noise gate threshold, then the noise gate is activated, causing the

signal path to be muted.

The noise gate function is enabled using the NGATE_ENA register, as described in Table 68.

For each output path, the noise gate may be associated with one or more of the signal path threshold

detection functions using the _NGATE_SRC register fields. When more than one signal threshold is

selected, then the output path noise gate is only activated (ie. muted) when all of the respective signal

thresholds are satisfied.

For example, if the OUT1L noise gate is associated with the OUT1L and OUT1R signal paths, then

the OUT1L signal path will only be muted if both the OUT1L and OUT1R signal levels are below the

respective thresholds.

The noise gate threshold (the signal level below which the noise gate is activated) is set using

NGATE_THR. Note that, for each output path, the noise gate threshold represents the signal level at

the respective output pin(s) - the threshold is therefore independent of the digital volume and PGA

gain settings.

Note that, although there is only one noise gate threshold level (NGATE_THR), each of the output

path noise gates may be activated independently, according to the respective signal content and the

associated threshold configuration(s).

To prevent erroneous triggering, a time delay is applied before the gate is activated; the noise gate is

only activated (ie. muted) when the output levels are below the applicable signal level threshold(s) for

longer than the noise gate

‘hold time’. The ‘hold time’ is set using the NGATE_HOLD register.

When the noise gate is activated, the WM8281 gradually attenuates the respective signal path at the

rate set by the OUT_VD_RAMP register (see Table 64). When the noise gate is de-activated, the

output volume increases at the rate set by the OUT_VI_RAMP register.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1043

(0413h)

Noise

Gate

Select 1L

11:0

OUT1L_NGATE_

SRC [11:0]

001h

Output Signal Path Noise Gate Source

Enables one of more signal paths as

inputs to the respective noise gate.

If more than one signal path is enabled as

an input, the noise gate is only activated

(ie. muted) when all of the respective

signal thresholds are satisfied.

[11] = OUT6R

[10] = OUT6L

[9] = OUT5R

[8] = OUT5L

[7] = OUT4R

[6] = OUT4L

[5] = OUT3R

[4] = OUT3L

[3] = OUT2R

[2] = OUT2L

[1] = OUT1R

[0] = OUT1L

Each bit is coded as:

0 = Disabled

1 = Enabled

R1047

(0417h)

Noise

Gate

Select 1R

11:0

OUT1R_NGATE_

SRC [11:0]

002h

R1051

(041Bh)

Noise

Gate

Select 2L

11:0

OUT2L_NGATE_

SRC [11:0]

004h

R1055

(041Fh)

Noise

Gate

Select 2R

11:0

OUT2R_NGATE_

SRC [11:0]

008h

R1059

(0423h)

Noise

Gate

Select 3L

11:0

OUT3L_NGATE_

SRC [11:0]

010h

R1063

(0427h)

Noise

Gate

Select 3R

11:0

OUT3R_NGATE_

SRC [11:0]

020h

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