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WM8281ECS/R Scheda tecnica(PDF) 198 Page - Cirrus Logic |
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WM8281ECS/R Scheda tecnica(HTML) 198 Page - Cirrus Logic |
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198 / 392 page ![]() WM8281 198 Rev 4.0 OUTPUT SIGNAL PATH AEC LOOPBACK The WM8281 incorporates loopback signal path, which is ideally suited as a reference for Acoustic Echo Cancellation (AEC) processing. Any of the output signal paths may be selected as the AEC loopback source. When configured with suitable DSP firmware, the WM8281 can provide an integrated AEC capability. The AEC loopback feature also enables convenient hook-up to an external device for implementing the required signal processing algorithms. The AEC Loopback source is connected after the respective digital volume controls, as illustrated in Figure 56. The AEC Loopback signal can be selected as input to any of the digital mixers within the WM8281 digital core. The sample rate for the AEC Loopback path is configured using the OUT_RATE register - see Table 23 within the “Digital Core” section. The AEC loopback function is enabled using the AEC_LOOPBACK_ENA register. The source signal for the Transmit Path AEC function is selected using the AEC_LOOPBACK_SRC register. The WM8281 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the AEC Loopback function. If an attempt is made to enable this function, and there are insufficient SYSCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected under these circumstances.) The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input / Output” and “Interrupts” for further details. The AEC_ENA_STS register indicates the status of the AEC Loopback function. If an Underclocked Error condition occurs, then this bit can provide indication of whether the AEC Loopback function has been successfully enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1104 (0450h) DAC AEC Control 1 5:2 AEC_LOOPBAC K_SRC [3:0] 0000 Input source for Tx AEC function 0000 = OUT1L 0001 = OUT1R 0010 = OUT2L 0011 = OUT2R 0100 = OUT3L 0101 = OUT3R 0110 = OUT4L 0111 = OUT4R 1000 = OUT5L 1001 = OUT5R 1010 = OUT6L 1011 = OUT6R All other codes are Reserved 1 AEC_ENA_STS 0 Transmit (Tx) Path AEC Control Status 0 = Disabled 1 = Enabled 0 AEC_LOOPBAC K_ENA 0 Transmit (Tx) Path AEC Control 0 = Disabled 1 = Enabled Table 69 Output Signal Path AEC Loopback Control |
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