WM8281ECSSLASHR datasheet(225/392 Pages) CIRRUS

225 / 392 page

WM8281

Rev 4.0

225

When a valid ‘Wake-Up’ event is detected, the WM8281 will enable LDO1 (and DCVDD), and a user-

configurable Boot Sequence is executed (see “Hardware Reset, Software Reset, Wake-Up, and

Device ID

”).

Note that the trigger status (_TRIG_STS) bits are latching fields. Care is required when resetting

these bits, to ensure the intended device behaviour - resetting the _TRIG_STS register(s) may cause

LDO1 (and DCVDD) to be disabled.

For normal device operation following a ‘Wake-Up’ transition, the LDO1_ENA register must be set (or

the LDOENA pin asserted) before the _TRIG_STS bit(s) are reset. (Note that further options are

described in the next section.)

For recommended use of the Sleep / Wake-Up functions, it is assumed that DCVDD is powered from

the output of LDO1 (see “Charge Pumps, Regulators and Voltage Reference”).

If DCVDD is powered externally (not from LDO1), then the JD1, GP5 and MICDET Clamp inputs

cannot trigger a Wake-Up transition directly; a Wake-Up transition will only occur by re-application of

DCVDD. In this configuration, the JD1, GP5 or MICDET Clamp inputs can provide a signal to the host

processor, via the IRQ

¯¯¯ output; if a Wake-Up transition is required, this can be implemented by the

host processor controlling the DCVDD supply.

If DCVDD is powered externally, then the WKUP_* control bits described in Table 84 must be held at

0 at all times.

WRITE SEQUENCE CONTROL

A Control Write Sequence can be associated with any of the JD1, GP5 or MICDET Clamp trigger

status bits. This is selected using the register bits described in Table 85.

Note that the JD1, GP5 and MICDET Clamp trigger status bits can be used to trigger the Control

Write Sequencer at any time. This feature may be used during normal operation, or immediately

following a Wake-Up transition.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R65 (0041h)

Sequence

Control

WSEQ_ENA_MICD_C

LAMP_FALL

MICDET Clamp (Falling) Write

Sequencer Select

0 = Disabled

1 = Enabled

WSEQ_ENA_MICD_C

LAMP_RISE

MICDET Clamp (Rising) Write

Sequencer Select

0 = Disabled

1 = Enabled

WSEQ_ENA_GP5_FA

GP5 (Falling) Write Sequencer

Select

0 = Disabled

1 = Enabled

WSEQ_ENA_GP5_RIS

GP5 (Rising) Write Sequencer

Select

0 = Disabled

1 = Enabled

WSEQ_ENA_JD1_FAL

JD1 (Falling) Write Sequencer

Select

0 = Disabled

1 = Enabled

WSEQ_ENA_JD1_RIS

JD1 (Rising) Write Sequencer

Select

0 = Disabled

1 = Enabled

Table 85 JD1, GP5 and MICDET Clamp Write Sequencer Control Registers

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