WM8281ECSSLASHR datasheet(228/392 Pages) CIRRUS

228 / 392 page

WM8281

228

Rev 4.0

GPIO CONTROL

For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO

pin (1, 2, 3, 4 or 5). The pin direction, set by GPn_DIR, must be set according to function selected by

GPn_FN.

When a pin is configured as a GPIO input (GPn_DIR = 1, GPn_FN = 01h), the logic level at the pin

can be read from the respective GPn_LVL bit. Note that GPn_LVL is not affected by the GPn_POL

bit.

A de-bounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled

on each pin by setting the respective GPn_DB bit. The de-bounce circuit uses the 32kHz clock, which

must be enabled whenever input de-bounce functions are required. The de-bounce time is

configurable using the GP_DBTIME register. See “Clocking and Sample Rates” for further details of

the WM8281 clocking configuration.

Each of the GPIO pins is an input to the Interrupt control circuit and can be used to trigger an Interrupt

event. An interrupt event is triggered on the rising and falling edges of the GPIO input. The associated

interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See

“Interrupts” for more details of the Interrupt event handling.

Integrated pull-up and pull-down resistors are provided on each of the GPIO pins; these can be

configured independently using the GPn_PU and GPn_PD fields. Note that, if GPn_PU and GPn_PD

are both set for any GPIO pin, then the pull-up and pull-down will be disabled.

When a pin is configured as a GPIO output (GPn_DIR = 0, GPn_FN = 01h), its level can be set to

logic 0 or logic 1 using the GPn_LVL field. Note that the GPn_LVL reg

isters are ‘write only’ when the

respective GPIO pin is configured as an output.

When a pin is configured as an output (GPn_DIR = 0), the polarity can be inverted using the

GPn_POL bit. When GPn_POL = 1, then the selected output function is inverted. In the case of Logic

Level output (GPn_FN = 01h), the external output will be the opposite logic level to GPn_LVL when

GPn_POL = 1.

A GPIO output can be either CMOS driven or Open Drain. This is selected on each pin using the

respective GPn_OP_CFG bit.

The register fields that control the GPIO pins are described in Table 86.

WM8281ECS/R Scheda tecnica(PDF) 228 Page - Cirrus Logic