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WM8281ECS/R Scheda tecnica(PDF) 229 Page - Cirrus Logic |
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WM8281ECS/R Scheda tecnica(HTML) 229 Page - Cirrus Logic |
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229 / 392 page ![]() WM8281 Rev 4.0 229 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3072 (0C00h) GPIO1 CTRL to R3076 (0C04h) GPIO5 CTRL 15 GPn_DIR 1 GPIOn Pin Direction 0 = Output 1 = Input 14 GPn_PU 0 GPIOn Pull-Up Enable 0 = Disabled 1 = Enabled 13 GPn_PD 1 GPIOn Pull-Down Enable 0 = Disabled 1 = Enabled 11 GPn_LVL 0 GPIOn level. Write to this bit to set a GPIO output. Read from this bit to read GPIO input level. For output functions only, when GPn_POL is set, the register is the opposite logic level to the external pin. Note that the GPn_LVL register is ‘write only’ when GPn_DIR=0. 10 GPn_POL 0 GPIOn Output Polarity Select 0 = Non-inverted (Active High) 1 = Inverted (Active Low) 9 GPn_OP_CFG 0 GPIOn Output Configuration 0 = CMOS 1 = Open Drain 8 GPn_DB 1 GPIOn Input De-bounce 0 = Disabled 1 = Enabled 6:0 GPn_FN [6:0] 01h GPIOn Pin Function (see Table 87 or Table 88 for details) R3088 (0C10h) GPIO Debounce Config 15:12 GP_DBTIME [3:0] 0001 GPIO Input de-bounce time 0h = 100us 1h = 1.5ms 2h = 3ms 3h = 6ms 4h = 12ms 5h = 24ms 6h = 48ms 7h = 96ms 8h = 192ms 9h = 384ms Ah = 768ms Bh to Fh = Reserved Note: n is a number (1, 2, 3, 4 or 5) that identifies the individual GPIO. Table 86 GPIO Control |
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