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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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WM8281ECS/R Scheda tecnica(PDF) 157 Page - Cirrus Logic |
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WM8281ECS/R Scheda tecnica(HTML) 157 Page - Cirrus Logic |
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157 / 392 page  WM8281 Rev 4.0 157 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1344 (0540h) AIF2 BCLK Ctrl 4:0 AIF2_BCLK_FRE Q [4:0] 01100 AIF2BCLK Rate 00000 = Reserved 00001 = Reserved 00010 = 64kHz (58.8kHz) 00011 = 96kHz (88.2kHz) 00100 = 128kHz (117.6kHz) 00101 = 192kHz (176.4kHz) 00110 = 256kHz (235.2kHz) 00111 = 384kHz (352.8kHz) 01000 = 512kHz (470.4kHz) 01001 = 768kHz (705.6kHz) 01010 = 1.024MHz (940.8kHz) 01011 = 1.536MHz (1.4112MHz) 01100 = 2.048MHz (1.8816MHz) 01101 = 3.072MHz (2.8824MHz) 01110 = 4.096MHz (3.7632MHz) 01111 = 6.144MHz (5.6448MHz) 10000 = 8.192MHz (7.5264MHz) 10001 = 12.288MHz (11.2896MHz) 10010 = 24.576MHz (22.5792MHz) The frequencies in brackets apply for 44.1kHz-related sample rates only. If AIF2_RATE<1000, then AIF2 is referenced to SYSCLK and the 44.1kHz- related frequencies apply if SAMPLE_RATE_n = 01XXX. If AIF2_RATE>=1000, then AIF2 is referenced to ASYNCCLK and the 44.1kHz-related frequencies apply if ASYNC_SAMPLE_RATE_n = 01XXX. The AIF2BCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as applicable. R1349 (0545h) AIF2 Tx BCLK Rate 12:0 AIF2TX_BCPF [12:0] 0040h AIF2TXLRCLK Rate This register selects the number of BCLK cycles per AIF2TXLRCLK frame. AIF2TXLRCLK clock = AIF2BCLK / AIF2TX_BCPF Integer (LSB = 1), Valid from 8..8191 R1350 (0546h) AIF2 Rx BCLK Rate 12:0 AIF2RX_BCPF [12:0] 0040h AIF2RXLRCLK Rate This register selects the number of BCLK cycles per AIF2RXLRCLK frame. AIF2RXLRCLK clock = AIF2BCLK / AIF2RX_BCPF Integer (LSB = 1), Valid from 8..8191 Table 38 AIF2 BCLK and LRCLK Control |
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