WM8281ECSSLASHR datasheet(159/392 Pages) CIRRUS

159 / 392 page

WM8281

Rev 4.0

159

AIF DIGITAL AUDIO DATA CONTROL

The register bits controlling the audio data format, word lengths and slot configurations for AIF1, AIF2

and AIF3 are described in Table 40, Table 41 and Table 42 respectively.

Note that Left-Justified and DSP-B modes are valid in Master mode only (ie. BCLK and LRCLK are

outputs from the WM8281).

The AIFn Slot Length is the number of BCLK cycles in one timeslot within the overall LRCLK frame.

The Word Length is the number of valid data bits within each timeslot. (If the word length is less than

the slot length, then there will be unused BCLK cycles at the end of each timeslot.) The AIFn word

length and slot length is independently selectable for the input (RX) and output (TX) paths.

For each AIF input (RX) and AIF output (TX) channel, the position of the audio data sample within the

LRCLK frame is configurable. The _SLOT registers define the timeslot position of the audio sample

for the associated audio channel. Valid selections are Slot 0 upwards. The timeslots are numbered as

illustrated in Figure 49 through to Figure 52.

Note that, in DSP modes, the timeslots are ordered consecutively from the start of the LRCLK frame.

In I2S and Left-Justified modes, the even-numbered timeslots are arranged in the first half of the

LRCLK frame, and the odd-numbered timeslots are arranged in the second half of the frame.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1284

(0504h)

AIF1

Format

2:0

AIF1_FMT [2:0]

000

AIF1 Audio Interface Format

000 = DSP Mode A

001 = DSP Mode B

010 = I2S mode

011 = Left Justified mode

Other codes are Reserved

R1287

(0507h)

AIF1

Frame Ctrl

13:8

AIF1TX_WL [5:0]

18h

AIF1 TX Word Length

(Number of valid data bits per slot)

Integer (LSB = 1); Valid from 16 to 32

7:0

AIF1TX_SLOT_L

EN [7:0]

18h

AIF1 TX Slot Length

(Number of BCLK cycles per slot)

Integer (LSB = 1); Valid from 16 to 128

R1288

(0508h)

AIF1

Frame Ctrl

13:8

AIF1RX_WL [5:0]

18h

AIF1 RX Word Length

(Number of valid data bits per slot)

Integer (LSB = 1); Valid from 16 to 32

7:0

AIF1RX_SLOT_L

EN [7:0]

18h

AIF1 RX Slot Length

(Number of BCLK cycles per slot)

Integer (LSB = 1); Valid from 16 to 128

R1289

(0509h)

R1296

(0510h)

5:0

AIF1TX1_SLOT

[5:0]

AIF1 TX Channel n Slot position

Defines the TX timeslot position of the

Channel n audio sample

Integer (LSB=1); Valid from 0 to 63

5:0

AIF1TX2_SLOT

[5:0]

5:0

AIF1TX3_SLOT

[5:0]

5:0

AIF1TX4_SLOT

[5:0]

5:0

AIF1TX5_SLOT

[5:0]

5:0

AIF1TX6_SLOT

[5:0]

5:0

AIF1TX7_SLOT

[5:0]

5:0

AIF1TX8_SLOT

[5:0]

R1297

(0511h)

R1304

5:0

AIF1RX1_SLOT

[5:0]

AIF1 RX Channel n Slot position

Defines the RX timeslot position of the

Channel n audio sample

Integer (LSB=1); Valid from 0 to 63

5:0

AIF1RX2_SLOT

[5:0]

5:0

AIF1RX3_SLOT

[5:0]

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