WM8281ECSSLASHR datasheet(201/392 Pages) CIRRUS

201 / 392 page

WM8281

Rev 4.0

201

WM8281

SPKOUTLN

SPKOUTLP

Left

SPKOUTRN

SPKOUTRP

Right

Figure 58 Speaker Connection

SPEAKER OUTPUTS (DIGITAL PDM)

The WM8281 supports a four-channel Pulse Density Modulation (PDM) digital speaker interface; the

PDM outputs are associated with the OUT5L, OUT5R, OUT6L and OUT6R output signal paths.

The PDM digital speaker interface comprises two stereo interfaces; the operation of one interface is

illustrated in Figure 59.

The OUT5L and OUT5R output signal paths are interleaved on the SPKDAT1 output pin, and clocked

using SPKCLK1. The OUT6L and OUT6R output signal paths are interleaved on the SPKDAT2 output

pin, and clocked using SPKCLK2.

Note that the PDM interface supports two different operating modes; these are selected using the

SPK1_FMT and SPK2_FMT register bits

. See “Signal Timing Requirements” for detailed timing

information in both modes.

When SPKn_FMT = 0 (Mode A), then the Left PDM channel is valid at the rising edge of SPKCLK; the

Right PDM channel is valid at the falling edge of SPKCLK.

When SPKn_FMT = 1 (Mode B), then the Left PDM channel is valid during the low phase of SPKCLK;

the Right PDM channel is valid during the high phase of SPKCLK.

SPKCLK output (Mode A)

SPKDAT output

(left & right channels interleaved)

Left channel output

Right channel output

SPKCLK output (Mode B)

Figure 59 Digital Speaker (PDM) Interface Timing

Clocking for the PDM interface is derived from SYSCLK. Note that the SYSCLK_ENA register must

also be set. See “Clocking and Sample Rates” for further details of the system clocks and control

registers.

When the OUT5L or OUT5R output signal path is enabled, the PDM interface clock signal is output on

the SPKCLK1 pin.

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