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WM8281ECS/R Scheda tecnica(PDF) 204 Page - Cirrus Logic

Il numero della parte WM8281ECS/R
Spiegazioni elettronici  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 204 Page - Cirrus Logic

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WM8281
204
Rev 4.0
EXTERNAL ACCESSORY DETECTION
The WM8281 provides external accessory detection functions which can sense the presence and
impedance of external components. This can be used to detect the insertion or removal of an external
headphone or headset, and to provide an indication of key/button push events.
Jack insertion is detected using the JACKDET pin, which must be connected to a switch contact
within the jack socket. An Interrupt event is generated whenever a jack insertion or jack removal event
is detected. The jack detect function can also be used to trigger a Wake-Up transition (ie. exit from
Sleep mode) and/or to trigger the Control Write Sequencer.
Suppression of pops and clicks caused by jack insertion or removal is provided using the MICDET
clamp function. This function can also be used to trigger interrupt events, a Wake-Up transition (ie.
exit from Sleep mode) and/or to trigger the Control Write Sequencer. The integrated General Purpose
Switch can be synchronised with the MICDET clamp, to provide additional pop suppression capability.
Microphones, push-buttons and other accessories can be detected via the MICDET1 or MICDET2
pins. The presence of a microphone, and the status of a hookswitch can be detected. This feature can
also be used to detect push-button operation.
Headphone impedance can be detected via the HPDETL and HPDETR pins; this can be used to set
different gain levels or other configuration settings according to the type of load connected. For
example, different settings may be applicable to Headphone or Line output loads.
The MICVDD power domain must be enabled when using the Microphone Detect function. (Note that
MICVDD is not required for the Jack Detect or Headphone Detect functions.) The MICVDD power
domain is provided using an internal Charge Pump (CP2) and LDO Regulator (LDO2). See “Charge
Pumps, Regulators and Voltage Reference
” for details of these circuits.
The internal 32kHz clock must be present and enabled when using the jack insertion or accessory
detection functions
; see “Clocking and Sample Rates” for details of the internal 32kHz clock and
associated register control fields.
JACK DETECT
The WM8281 provides support for jack insertion switch detection. The jack insertion status can be
read using the relevant register status bit. A jack insertion or removal can also be used to trigger an
interrupt (IRQ) event or to trigger the Control Write Sequencer.
When the WM8281 is in the low-power
Sleep mode (see “Low Power Sleep Configuration”), the jack
detect function can be used as a ‘wake-up’ input; a typical use case is where an application is idle in
standby mode until a headphone or headset jack is inserted.
Jack insertion and removal is detected using the JACKDET pin. The recommended external
connection circuit is illustrated in Figure 61.
The jack detect feature is enabled using JD1_ENA; the jack insertion status can be read using the
JD1_STS register.
The JACKDET input de-bounce is selected using the JD1_DB register, as described in Table 75. Note
that the de-bounce circuit uses the 32kHz clock, which must be enabled whenever input de-bounce
functions are required.
Note that the Jack Detect signal, JD1, can be used as an input to the MICDET Clamp function. This
provides additional functionality relating to jack insertion or jack removal events.
An Interrupt Request (IRQ) event is generated whenever a jack insertion or jack removal is detected
(see “Interrupts”). Separate ‘mask’ bits are provided to enable IRQ events on the rising and/or falling
edge of the JD1 status.
The Control Write Sequencer can be triggered by a jack insertion or jack removal detection. This is
enabled using register bits described in the “Low Power Sleep Configuration” section.
The control registers associated with the Jack Detect function are described in Table 75.



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